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AgeCommit message (Expand)Author
2009-12-15ARM: specify PMD cacheable attributes correctly for SMPGary King
2009-12-15ARM: fix broken mergeGary King
2009-12-15ARM: add tegra as a valid dependency for CPU_V6 and CPU_V7Gary King
2009-12-14ARM: change PRRR remappingGary King
2009-12-14ARM: clear exclusive monitor when exiting switch_mmGary King
2009-12-14ARM: implement SMP- and L2-aware _fin for ARMv7 processorsGary King
2009-12-14ARM: add NVIDIA Tegra AP15/AP16 processor supportGary King
2009-12-08l2x0: add deinit routine to safely disable the cacheGary King
2009-12-08cherry-pick commit 6dd5056b9abe1e38fae... from arm-devel.org/develGary King
2009-12-08ARM: Add kmap_atomic type debuggingRussell King
2009-12-08ARM: 5691/1: fix cache aliasing issues between kmap() and kmap_atomic() with ...Nicolas Pitre
2009-12-08[ARM] introduce dma_cache_maint_page()Nicolas Pitre
2009-12-08cherry-pick commit d73cd42893f4cdc06e682 from linux-arm.org/develGary King
2009-12-08Fix broken merge from linux-arm.org/arm-2.2.28 branchGary King
2009-12-07Flush the D-cache during copy_user_highpage()Catalin Marinas
2009-12-07Cherry-pick commit f4ac102a1f66ae4fb3942ac5c41bc1f2923b4730Gary King
2009-12-07Merge commit 'arm/2.6.28-arm' into android-tegra-2.6.29Gary King
2009-10-26ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line sizeKirill A. Shutemov
2009-10-12[ARM] force dcache flush if dcache_dirty bit setNitin Gupta
2009-09-23Remove the cpu_isset() check in flush_ptrace_access()Catalin Marinas
2009-09-23Flush the D-cache during copy_user_highpage()Catalin Marinas
2009-09-23Handle possible translation errors in the ARMv6 and ARMv7 coherent userCatalin Marinas
2009-09-23Revert the mprotect cacheflush fixCatalin Marinas
2009-09-09Add "nol2x0" early param to avoid initialisation of the L2 controllerCatalin Marinas
2009-09-08Flush the user cache range if page protection is changed via mprotectCatalin Marinas
2009-09-08Cortex-M3: Add support for the Microcontroller Prototyping SystemCatalin Marinas
2009-09-08Cortex-M3: Allow the building of Cortex-M3 kernel portCatalin Marinas
2009-09-08Cortex-M3: Add base support for Cortex-M3Catalin Marinas
2009-09-02[ARM] 5540/1: 32-bit Thumb-2 {ld,st}{m,rd} alignment fault fixup supportMin Zhang
2009-09-02ARMv7: Make SWP always enabled on Cortex-A9Catalin Marinas
2009-09-02ARMv7: Mark PTWs outer non-shareable on SMPCatalin Marinas
2009-09-01ARMv6: Updated the BE-8 patch to be in sync with the mainline kernelCatalin Marinas
2009-06-10[ARM] Optionally flush entire dcache from v6_dma_flush_rangeArve Hjønnevåg
2009-03-31ARMv7: Enable the ACTLR.FW bit to enable TLB ops broadcasting on SMPCatalin Marinas
2009-03-12[ARM] Fix virtual to physical translation macro corner casesRussell King
2009-03-12[ARM] 5421/1: ftrace: fix crash due to tracing of __naked functionsUwe Kleine-König
2009-03-10Eviction Buffer not empty after Cache Sync on the L220 cache controllerCatalin Marinas
2009-03-10Data written to the L2 cache can be overwritten with stale data on Cortex-A8Catalin Marinas
2009-03-10Processor deadlock when a false hazard is created on Cortex-A8Catalin Marinas
2009-03-10Stale prediction on replaced interworking branch on Cortex-A8Catalin Marinas
2009-03-10Workaround for the global I cache invalidation ARM1136 ErrataCatalin Marinas
2009-03-10Enable partial low interrupt latency mode for ARM1136Catalin Marinas
2009-03-10Thumb-2: Add IT instructions to the kernel assembly codeCatalin Marinas
2009-03-10Thumb-2: Implement the unified arch/arm/mm supportCatalin Marinas
2009-03-10nommu: Do not set PRRR and NMRR in proc-v7.S if !MMUCatalin Marinas
2009-03-10nommu: Add #ifdef CONFIG_MMU around the PTE sanity checksCatalin Marinas
2009-03-10nommu: Include asm/setup.h in arch/arm/mm/nommu.cCatalin Marinas
2009-03-10nommu: Add noMMU support to the DMA APICatalin Marinas
2009-03-10nommu: Fix the fault processing for the MMU-less caseCatalin Marinas
2009-03-10Allow the L2x0 cache controller to be already initialisedCatalin Marinas
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