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2012-09-03ENGR00222855 MX6 CPUFREQ: support three VDDSOC setpointsrel_imx_3.0.35_12.09.02Robin Gong
On MX6Q/DL , there is only two set point of VDDSOC/VDDPU, one is 1.25V(1GHz), another is 1.175V. And in arch/arm/plat-mxc/cpufreq.c will judge whether the current cpu frequency is the highest set point(1G) or not to set the right VDDSOC/VDDPU. The logic is also match to dynamic ldo bypass function, since the change point is the highest set point too. But there is three set points of VDDSOC/VDDPU in MX6SL , so the logic in cpufreq.c need to change. Now VDDSOC/VDDPU will track with VDDARM fully. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-08-31ENGR00222133 MX6SL - Fix crashes caused by Low power IDLE supportRanjani Vaidyanathan
Need to ensure that the ARM_CLK rate stays exactly the same when moving ARM_CLK from PLL2_PFD_400 to PLL1 when system enters 24MHz state. Also need to ensure that PLL1 is enabled before relocking the PLL to the correct rate. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-29ENGR00221975 Fix race condition in clock code.Ranjani Vaidyanathan
Need to ensure that check for usecount in clk_set_parent occurs within the protection of the clock mutex. Else there is a chance that the usecount can be decremented (and the clock disabled) after the check. Also add back the code to maintain the correct usecount for pll2_pfd_400. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-30ENGR00221902 [MX6]Fix udelay inaccurate issue during suspend/resumeAnson Huang
When system enter suspend, we increase CPUFreq to the highest point without update the global loops_per_jiffy, it will lead to udelay inaccurate during the last phase of suspend/resume. WB counter and RBC counter need at least two 32K cycles to finish, here we add 80us for safe. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-29ENGR00221716-02 Mx6 USB host: add port speed define MACRO to arc_otg.hmake shi
Add port speed define MACRO to arc_otg.h. Signed-off-by: make shi <b15407@freescale.com>
2012-08-28ENGR00221302 [MX6SL_ARM2/EVK]: VDDSOC adjust if use LDO bypassRobin Gong
The function has been implement in LDO enable , but not in LDO bypass. Implement it on mx6sl. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-08-26ENGR00221440 MX6x-Fix race-condition in checking bus_freq variablesRanjani Vaidyanathan
Checking of the bus_freq variables and changing of the bus/ddr frequency should be done under one mutex. Else there is a race-condition that the variable changed just after it was checked. Also ensure that the bus freq is always increased before the cpu freq is set to anything other than the lowest setpoint. Else there is a possibility that the ARM is set to run from PLL1 at higher frequency when bus/DDR are still at 24MHz. This is dangerous since when system enters WAIT mode in low bus freq state, PLL1 is set to bypass when ARM is being sourced from it. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-24ENGR00220796-3: imx6sl arm2/evk: Add platform_device for V4L2 supportRobby Cai
Add platform device for V4L2 support Signed-off-by: Robby Cai <R63905@freescale.com>
2012-08-24ENGR00221317-02 Mx6 USB host: set stop_mode_config when any USB host enabledmake shi
The Mx6 phy sometimes work abnormally after system suspend/resume if the 1V1 is off. So we should keep the 1V1 active during the system suspend if any USB host enabled. - Add stop_mode_config to 1 with refcount - Add mutex to protect the refcount and HW_ANADIG_ANA_MISC0 register - If stop_mode_config is set as 1, the otg vbus wakeup system will be supported Signed-off-by: make shi <b15407@freescale.com>
2012-08-23ENGR00221214 MX6Q/DL SabreSD: avoid pop-noise on audio padsGary Zhang
config audio pads to avoid pop-noise Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-08-22ENGR00220370 [MX6]Fix BUS freq suspend/resume fail in low bus modeAnson Huang
1. BUS freq's set low bus setpoint using delat work, which didn't have mutex lock, so in some scenarios, set high bus freq function can be called at the same time, we need to move mutex lock into these two routine; 2. Using pm notify to make sure bus freq set to high setpoint before supend and restore after resume. 3. Clear build warning. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-17ENGR00220027-2 mx6sl: add pad ctrl for audmux iomux settingGary Zhang
for avoiding pop-noise adn setting audmux pad to 1.8v on evk, add pad ctrl for audmux iomux setting Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-08-17ENGR00220027-1 IOMUX: add api for special pad bits configurationGary Zhang
Original pad configuration does not provide enough bitfield width to config some bits, such as LVE bit and DDR_SEL bits. like gpr configuration, add a api to implement these special bits pad configuration, and user may call this api in board file. Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-08-16ENGR00220341-1 usb: add spin_lock_irqsave protect for pdata->lowpowerPeter Chen
pdata->lowpower may be accessed at two drivers together, assumed the situation that host/device set phy to low power mode but still not set the flag lowpower, at this time the wakeup occurs, as the flag lowpower is still not set, the interrupt will be infinite loop as no one will serve it. This commit is for MSL code and add protect at wakeup interrupt. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-08-15ENGR00220161: imx6sl: Add EVK board SupportRobby Cai
- Copied the board file from ARM2, and consolidated the pinmux setting. - Added a new pmic file for EVK. - Added a new mach type. - Added board_is_mx6sl_evk() API for late use if needed. - Updated the defconfig Signed-off-by: Robby Cai <R63905@freescale.com>
2012-08-15ENGR00219856-2 mxc pwm: do pwm software reset after disableXinyu Chen
When android doing suspend/resume, we may meet the issue of backlight is not on (pwm pin no signal) after system wakeup. The root cause is PWM sample can not be set into the PWMSAR register after pwm being used and disabled for a while. The value read back after write is 0 when this issue happens. Do a software reset after pwm disable can resolve this issue, this makes sure the next sample update is correct. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
2012-08-14ENGR00220340 mx6sl pfuze: keep NVCC_1V8 and NVCC_1.2V always onRobin Gong
1. Keep the corresponding rail of pfuze:VGEN4 and VGEN1 "always on". 2. mx6sl enable LDO bypass default, which can't including adjust soc and pu regulator. To support old LDO bypass code, need check soc_regulator and pu_regulator, otherwise, system will crash. Signed-off-by: Robin Gong <b38343@freescale.com>
2012-08-13ENGR00220154 GPT mx6: move mx6_timer_rate to clock.cRobin Gong
System will report oops as below. To fix it we will move mx6_timer_rate to clock.c, so that we can avoid use clk_get_sys which cause schedule after spin_lock. oops log: BUG: scheduling while atomic: kinteractiveup/1403/0x00000002 Modules linked in: (unwind_backtrace+0x0/0xfc) from [<804f05f0>] (__schedule+0x4b8/0x6b0) (__schedule+0x4b8/0x6b0) from [<804f12ac>] (__mutex_lock_slowpath+0x138/0x208) (__mutex_lock_slowpath+0x138/0x208) from [<804f13b4>] (mutex_lock+0x38/0x3c) mutex_lock+0x38/0x3c) from [<803b9134>] (clk_get_sys+0x1c/0xec) (clk_get_sys+0x1c/0xec) from [<8005f814>] (mx6_timer_rate+0x14/0x7c) (mx6_timer_rate+0x14/0x7c) from [<80056a20>] (_clk_gpt_get_rate+0x18/0x2c) (_clk_gpt_get_rate+0x18/0x2c) from [<8005e89c>] (clk_get_rate+0x34/0x40) (clk_get_rate+0x34/0x40) from [<80055f3c>] (_clk_pll_enable+0xa8/0x1ec) (_clk_pll_enable+0xa8/0x1ec) from [<80056088>] (_clk_pll1_enable+0x8/0x20) (_clk_pll1_enable+0x8/0x20) from [<80056998>] (_clk_arm_set_rate+0x278/0x2e8) (_clk_arm_set_rate+0x278/0x2e8) from [<8005e824>] (clk_set_rate+0x54/0x68) (clk_set_rate+0x54/0x68) from [<80061660>] (set_cpu_freq+0xb8/0x160) (set_cpu_freq+0xb8/0x160) from [<800618b4>] (mxc_set_target+0xf0/0x20c) (mxc_set_target+0xf0/0x20c) from [<80372388>](__cpufreq_driver_target+0x54/0x60) Signed-off-by: Robin Gong <b38343@freescale.com>
2012-08-13ENGR00220153 cpufreq mx6: new cpu set point and add VDDSOC/PU adjustRobin Gong
1.add new cpu setpoint: replace 498Mhz with 672Mhz,and remove 198Mhz. but now 498Mhz seems not stable enough, comment now, test enough to add it. Rigel kept unchange now. 2.support adjusting VDDSOC/VDDPU when cpu frequency change. Signed-off-by: Robin Gong <b38343@freescale.com>
2012-08-11ENGR00220022 [MX6]Add necessary protection to bus freq variables and functionAnson Huang
All bus freq related variables and function calls need to be protected by mutex, or these variables may be wrong and result in triggering bus freq change by mistake, it will impact many modules function. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-01ENGR00218810-1 [Thermal]Add thermal alarm functionAnson Huang
Add thermal irq alarm function. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-07-30ENGR00218747 - MX6Q/MX6DL: WAIT mode support for MX6QTO1.2/MX6DLTO1.1Ranjani Vaidyanathan
Add the new WAIT mode workaround added for MX6Q1.2 and MX6DLTO1.1. A new bit is added to CCM_CGPR (bit 17). This bit needs to be enabled for the WAIT mode fix to be active and needs to be disabled before the system enters STOP mode with power gating enabled. Fix WAIT mode bug when system is in low power IDLE mode: In low power IDLE mode (AHB @ 24MHz), switch ARM to run from 24MHz on MX6QTO1.1 and MX6DLTO1.0 chips when ARM core enters WAIT mode. We still need to use the ARM:IPG_CLK ratio of 12:5. Since IPG_CLK is at 12MHz, we need to run ARM below 28.8MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-07-30ENGR00218771 mx6 USB:USB disconnect issue verification on MX6QTO1.2/MX6DLTO1.1make shi
- for Rigel1.1/Arik1.2, bit 17 of HW_USBPHY_IP will be set, it will fix the issue that no wakeup between SUSP/PHCD. And the usb_platform_rh_suspend/ usb_platform_rh_resume do not need do complex software workaround, only need set/clear the workaround bit. - for Megrez , bit 17 and bit 18 of HW_USBPHY_IP will be set, it will fix the issue that no wakeup between SUSP/PHCD and disconnect after resume. No need do any software workaround. Signed-off-by: make shi <b15407@freescale.com>
2012-07-30ENGR00218013-2 SDMA:Add script address for HDMIChen Liangjun
Add hdmi-sdma script enum type for SDMA script. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-07-30ENGR00218013-1 DMA:Add HDMI DMA type and priv data for imx_dma_dataChen Liangjun
1 Add HDMI sdma periphal enum type. 2 Add private data type for imx_dma_data. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-07-26ENGR00215520-03 Mx6:USB host: USB Host1 modulizationmake shi
- remove mx6_usb_h1_init() in board specific initialization files - Add module_init(mx6_usb_h1_init) and module_exit(mx6_usb_h1_exit) in usb_h1.c to support the usb_h1 modulization - Export necessary function which is used in usb_h1.c Signed-off-by: make shi <b15407@freescale.com>
2012-07-25ENGR00216270-1 MXC EDID add HDMI VSDB variableSandor Yu
Define more variable in struct mxc_edid_cfg for HDMI VSDB. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-07-25ENGR00217306-2: Add DCP/RNGB arch supportTerry Lv
This patch will add arch support of DCP/RNGB. Signed-off-by: Terry Lv <r65388@freescale.com>
2012-07-25ENGR00216013-3 vpu: add VPU_IOC_PHYMEM_CHECK ioctl.Zhang Jiejing
Add VPU_IOC_PHYMEM_CHECK ioctl in header file. This IOCTL will check the phy memory address is valid or not. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-07-25ENGR00216955 MX6 General : Fix a typo when defining OCOTP fuse nameEric Sun
The name in BANK2, "SOTPMK1" should be "OTPMK1" Signed-off-by: Eric Sun <jian.sun@freescale.com>
2012-07-25ENGR00216001 MX6 Kernel : Fix a typo when defining "IO_ADDRESS" macroEric Sun
When defining macro "IO_ADDRESS", the address is checked against PERIPH address. ((x) <= (unsigned long)(ARM_PERIPHBASE + ARM_PERIPHBASE)) ... The second "ARM_PERIPHBASE" is obviously a typo, should changed to ARM_PERIPHBASE_SIZE Signed-off-by: Eric Sun <jian.sun@freescale.com> Signed-off-by: Garg Nitin <b37173@freescale.com>
2012-07-25ENGR00215668 [MX6]Only restore PU field value instead of whole reg valueAnson Huang
Only need to save and restore PU field register value instead of the whole CORE REG value to avoid changing SOC and ARM voltage. No need to increase BUS freq before CPU freq increase when system is in audio bus mode. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-07-20ENGR00213014-8 HDMI: add head define for HDMI HDCPSandor Yu
Added HDMI I2C Master register define and bit setting. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-07-20ENGR00213014-6 MXC EDID: define mxc_edid_parse_ext_blk functionSandor Yu
added function mxc_edid_parse_ext_blk defined. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-07-20ENGR00213014-4 HDMI HDCP: IOMUX define for MX6XSandor Yu
Added IOMUX and pad setting for HDMI DDC for mx6q/mx6dl. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-07-20ENGR00215182-1 sabresd: Add basic support for HDMI CECZhang Xiaodong
- Changes to IOMUX to allow HDMI CEC controller to use KEY_ROW2 pin that it needs - Add cec device in platform-mxc_hdmi.c - Add MXC_HDMI_CEC in imx6_defconfig Signed-off-by: Zhang Xiaodong <B39117@freescale.com>
2012-07-20ENGR00215491 [MX6]Need to increase BUS freq when CPU freq is increasedAnson Huang
When BUS freq is running at DLL off mode(24M or 50M), when CPU freq is increased, we need to increase BUS freq to 400M setpoint in order to achieve high performance when CPU is busy. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-07-20ENGR00215489-2 WDOG :add watchdog irq in device structureRobin Gong
1.add watchdog irq in device structure 2.modify watchdog irq macro define to meet _SOC_ Signed-off-by: Robin Gong <B38343@freescale.com>
2012-07-20ENGR00215188-1 PFUZE CPUFREQ: reconstruct LDO bypass functionRobin Gong
As before, raw I2C operation is added in suspend interface of cpufeq driver,so that we can raise up cpu frequency and voltage after I2C driver suspended.But the code is not platform independent if customer use another pmic whose I2C slave address is different with pfuze. Now, we rasie up cpu frequency and disable cpu frequency change in more earlier than before. If system begin to suspend flow, we will do this. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-07-20ENGR00214813 MX6DL SabreSD : Kernel, Enable ARM Perfromance MonitorEric Sun
Register PMU resources during system bootup, so that "Perf" Command can be used to get misc performance data of a running program The "Perf" Exe should be built manually in "./tools/perf" using the following command line > make CROSS_COMPILER=... ARCH=arm CFLAGS="-static -DGElf_Nhdr=Elf32_Nhdr" then copy the "Perf" executable to rootfs/bin Usage : perf # show help content perf list # show all available statistics options perf stat ls # show all statistics of a "ls" command perf stat -e cycles tar cvfz bin.tgz /bin # show "cycles" statistics of command # "tar cvfz ...." MX6 Series Chips bound all CPUs PERFMON IRQ to one, this may cause some problems when get per-CPU statistics. Need further investigation Signed-off-by: Eric Sun <jian.sun@freescale.com>
2012-07-20ENGR00214791-1 [MX6] Add baseAddress parameter for GPU resourceLarry Li
Add baseAddress parameter for GPU resource according to different SOC Signed-off-by: Larry Li <b20787@freescale.com>
2012-07-20ENGR00213944-02: mmc: sdhci: [MX6] support SD v3.0 memory cards.Ryan QIAN
- Add variable pad speed setting per SD clk freq. - Add SD3.0 support on SD1, SD2, and SD3. - Enhance drive strength on SD pad to improve its compatibility. - change the definition of pad speed changing interface - combine pad speed setting for different SD host controllers into one function. Signed-off-by: Ryan QIAN <b32804@freescale.com> Acked-by: Lily Zhang
2012-07-20ENGR00213903 [MX6]Improve periph parent change flowAnson Huang
When bus freq is changed, we need to update periph clk's parent, better to use clk_set_parent API instead of changing the parent directly. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-07-20ENGR00213751: imx6sl: Add ELAN touchscreen support on EINK-DC3 boardRobby Cai
Add ELAN capacitive TS support on EINK-DC3 stacked on MX6SL_ARM2 board - configure the iomux setting (need 4.7K Ohm pull up on 'touch_int_b') - configure the i2c slave addr - configure the GPIO setting for ELAN ce/int/rst - update the defconfig Signed-off-by: Robby Cai <R63905@freescale.com>
2012-07-20ENGR00213749: imx6sl: Add keypad support on EINK-DC3 boardRobby Cai
Add the support for keypad on EINK-DC3 board which is stacked on ARM2 board. - configure the iomux setting - add dummy kpp clock to fool imx_keypad driver - add platform device for keypad - add key mapping (4x4 array) used on EINK-DC3 - update the defconfig for keypad driver Signed-off-by: Robby Cai <R63905@freescale.com>
2012-07-20ENGR00213684 MX6DL: emmc: mx6dl needs more iomux strength to emmc.Zhang Jiejing
this patch add more iomux strength to mx6dl's emmc. otherwise, -110 error when access emmc will occures. current test show this patch can improve on this issue. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-07-20ENGR00213158-1 IPU: Add IPU oneshot interrupt modeWayne Zou
Add IPU oneshot interrupt mode: IPU_IRQF_ONESHOT. Interrupt is not reenabled after irq handler finished. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-07-20ENGR00213170-1 [MX6SL] Add resource needed by GPULarry Li
Prepare resourec such as memory, interrupt, clock, regester address needed by GPU. Signed-off-by: Larry Li <b20787@freescale.com>
2012-07-20ENGR00180919 [MX6]Update clock tree if BUS freq is changedAnson Huang
As DDR freq change is by modifying CCM register directly, we need to update the clock tree as well, or the clock tree will be broken. Also, we need to make sure the clock rate counting is right. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-07-20ENGR00211670- CPUFREQ-Set CPU to maximum frequency before entering STOP modeRanjani Vaidyanathan
Ensure that the CPUFREQ driver sets the CPU to its maximum frequency when it is suspended. Also change the WAIT macro in clock.c to use GPT counter for the delay instead of getnsdayoftime(). As the kernel timekeeping driver is suspended before CPUFREQ and this causes a dump during suspend. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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