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2019-02-12MLK-16976-2 ARM64: dts: fsl-imx8qm: let USB have wakeup capabilityPeter Chen
Let PM code know USB has wake system up capability. BuildInfo: - SCFW 245582b, IMX-MKIMAGE 0ad6069a, ATF 6bd98a3 - U-Boot 2017.03-imx_v2017.03+gfa65b0a Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-16976-1 ARM64: dts: fsl-imx8: add OTG register regions for Cadence USB3Peter Chen
Add OTG register regions for Cadence USB3. BuildInfo: - SCFW 245582b, IMX-MKIMAGE 0ad6069a, ATF 6bd98a3 - U-Boot 2017.03-imx_v2017.03+gfa65b0a Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-17072-2: ARM64: dts: freescale: imx8qm/qxp: enable MU as wakeup sourceRobin Gong
Enable MU as wakeup source in dts. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
2019-02-12MLK-16973-6 arm64: dtsi: fsl-imx8qm: Add lvds0/1_pwm nodesLiu Ying
This patch adds lvds0/1_pwm device tree nodes for the i.MX8QM SoC. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2019-02-12MLK-16938 ARM64: dts: imx8: refine the imx8 dtsRichard Zhu
- Add the clk_req property for imx8 pcie, make sure that the clk_req would be active. - Correct the spell mistake of pcie pinctrl on imx8qxp. - Fix the potential conflication with the usage of SC MU, remove the useless "fsl,imx8-mu" of rpmsg. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-16918-8: arm64: dtsi: fsl-imx8qm: Update dtsi for nwl-mipi-dsiRobert Chiras
Now, the NWL MIPI-DSI driver is implemented as a real bridge and uses the "nwl,mipi-dsi" compatible. This patch updates the mipi-dsi nodes to comply with the new design of NWL and NWL_IMX drivers. Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
2019-02-12MLK-16818-1 ARM64: dts: imx8: modify the dts to enable ep rc supportRichard Zhu
- Correct the comments of iMX8QM PCIEB - Enlarge the CFG space of iMX8QXP PCIEB. - PCIE port maybe hard-wired in the hardware design. Use the hard-wired property to specify it on iMX8MQ. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-16839-2: ARM64: dts: add clock source for asrcShengjiu Wang
add IMX8QM_ACM_AUD_CLK0_SEL and IMX8QM_ACM_AUD_CLK1_SEL for asrc clock source. There is no clock gate for them, only clock mux. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-02-12MLK-16765-7 ARM64: dts: freescale: fsl-imx8qm: enable PWRON key in dtsRobin Gong
Enable PWRON key in dts. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-16817-1 ARM64: imx: add the pcie per clk for imx8qm/qxpRichard Zhu
Add the pcie per clk for imx8qm/qxp. Since it is mandatory required in imx8qm/qxp pcie pm. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-16347-7: arm64: dtsi: fsl-imx8qm: Add mipi-dsi specific nodesRobert Chiras
Add support for mipi-dsi DRM driver in DTS files for i.MX8qm platform. Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
2019-02-12MLK-16742-3: dts: arm64: imx8qm: Fix ESAI fsys clock.Viorel Suman
Set ESAI fsys clock to IMX8QM_AUD_ESAI_0_IPG. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-02-12MLK-16754 ARM64: dts: imx8qm: enable the smmu on sataRichard Zhu
enable the smmu on sata BuildInfo: - SCFW 9559d5ec, IMX-MKIMAGE 06bc2767, ATF - U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-16704-2: ARM64: dts: freescale: imx8qm/qxp: add watchdogRobin Gong
add watchdog in dts. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-16705-2 ARM64: dts: freescale: imx8qm: add resource wakeup supportAnson Huang
Add wakeup unit to support resource wakeup management on i.MX8QM, also enable wakeup function for LPUARTx. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-16684-1 ARM: dts: enable imx8qm sataRichard Zhu
- enable imx8qm sata. - correct sata power supply. - sata clks: satahost_clk hsio_lpcg_sata phyx1_pclk phyx1_lpcg phyx1_epcs_tx_clk phyx1_lpcg hyx1_epcs_rx_clk phyx1_lpcg phyx2_pclk0 phyx2_lpcg phyx2_pclk1 phyx2_lpcg BuildInfo: - SCFW 9559d5ec, IMX-MKIMAGE 06bc2767, ATF - U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f Reviewed-by: Frank Li <frank.li@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-16690 ARM64: dts: freescale: imx8qm: update A53 cpu-freq tableAnson Huang
SCFW removes A53 1.26GHz cpu-freq set-point, update it for linux kernel cpu-freq driver accordingly. SCFW patch: (674c078 Fix CPU frequency related issues) Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-16676-2 ARM64: dts: freescale: imx8qm: add early_power_on for intmuxAnson Huang
On i.MX8QM, intmux is registered as irq chip driver, it resumes earlier then generic power domain, so need to add early_power_on property. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-16606-2 arm64: dts: imx8qm: add M40 and M41 I2C devicesDong Aisheng
add M40 and M41 I2C devices Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2019-02-12MLK-16586-2 ARM64: dts: imx: enable multi-core rpmsg supportRichard Zhu
Because there are two m4 cores on imx8qm, enable imx8qm multi-core rpmsg support BuildInfo: - SCFW a6fd9a48, IMX-MKIMAGE 0, ATF 0 - U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936c Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Andy Duan <fugang.duan@nxp.com> Tested-by: Andy Duan <fugang.duan@nxp.com>
2019-02-12MLK-16571-3: arm64: dts: add i.MX8QM lpspi device nodeHan Xu
add the lpspi device node and change the peripheral to nor chip. i.MX8QM also need both ipg and per clock for this module. BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0 Reviewed-by: Pan Gao <pandy.gao@nxp.com> Signed-off-by: Han Xu <han.xu@nxp.com>
2019-02-12MLK-13946-5: ARM64: dts: enable dp audio for imx8qmShengjiu Wang
Enable dp audio for imx8qm, define sai hdmi tx and rx node. use property "procotol" to replace the "video-mode" Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-02-12MLK-16530-1 ARM64: dts: imx8: enable rpmsg supportRichard Zhu
enable imx8qm rpmsg support, and validated the pingpong demo. add the mu power and clk on imx8qxp. BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0 Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-16538-6: dts: Add hdmi property to imx8qm dtsSandor Yu
-Add hdmi property item to imx8qm dts file. -Connect hdmi to dpu1_disp0 port. -Remove unnecessary clk from hdmi steer irq property. -Fix typo for irqsteer_csi0 Acked-by: Robby Cai <robby.cai@nxp.com> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2019-02-12MLK-16056 clk: imx8qm: add new dsi clocksRobert Chiras
Add clk for dsi0-i2c1, dsi1-i2c0 and dsi1-i2c1 Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
2019-02-12MLK-16442-3: dts: imx8qm: Add clock parents for DC clocks.Adriana Reus
Adds dt settings for the dpu driver to set the default clock parents - PLL1 (dc0_pll0_clk) for dispay0 and PLL2(dc0_pll1_clk) for display1. Functionality is not changed from dpu driver perspective as the same parents for the display clocks were used before. The resulting clock topology for dc0_disp1 is: dc0_pll1_div 1 1 1188000000 0 0 dc0_pll1_clk 2 2 1188000000 0 0 dc0_disp1_sel 1 1 1188000000 0 0 dc0_disp1_div 1 1 148500000 0 0 dc0_disp1_clk 1 1 148500000 0 0 (BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0) Signed-off-by: Adriana Reus <adriana.reus@nxp.com> Reviewed by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
2019-02-12MLK-16359-1: Added i.MX8 CAST IP JPEG Encoder/Decoder Linux to DTSZhengyu Shen
Adds device tree files for JPEG decoder and encoder to device tree. Signed-off-by: Zhengyu Shen <zhengyu.shen_1@nxp.com> Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
2019-02-12MLK-16471-02 arm64: dts: imx8qm/imx8qxp: remove ptp clock from assigned-clocksFugang Duan
Since IMX8QXP_ENET0_ROOT_DIV clock is included in assigned-clocks list, and who is the parent of IMX8QXP_ENET0_PTP_CLK (ptp clock), so remove ptp clock from assigned-clocks list. (BuildInfo: SCFW 3e70523d, IMX-MKIMAGE 0, ATF 0) Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-16354-2 ARM64: dts: imx8qm: add usdhc support for IOMMUHaibo Chen
add usdhc1/usdhc2/usdhc3 support for IOMMU Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2019-02-12MLK-16372-4 arm64: dts: imx8qm: add cpu-freq cooling mapAnson Huang
Add i.MX8QM cpu-freq cooling support, when temperature exceeds passive point, cpu-freq will drop to lowest set-point. Both A53 and A72 cluster are supported. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-16327-2: ARM64: dts: fsl-imx8qm/qxp: correct edma channel nameRobin Gong
Correct edma channel name to support unique edma channel name in multi edma instances. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-02-12MLK-16286-1 arm64: dts: freescale: imx8qm: add cpu opp tableAnson Huang
Add i.MX8QM CPU OPP table to support cpu-freq. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-16065-1 ARM64: dts: fsl-imx8qm.dtsi: add Cadence USB3 supportPeter Chen
Add Cadence USB3 controller and phy, the phy uses generic USB PHY driver. Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-16204-2 arm64: dts: add ocotp nodePeng Fan
Add ocotp node. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-02-12MLK-16172: dts: imx8qm: Add pwm entriesAdriana Reus
Add entries for imx8qm pwms. DT settings were tested on zebu. Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
2019-02-12MLK-16126 arm64: dts: imx8qm: Fix pd_sata0 node's nameYe Li
Should use PD_HSIO_SATA_0 not the PD_HSIO_SATA0 to align with imx8_pd.h. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-02-12arm64: dts: freescale: imx8qm: add reserve memory for rpmsgAnson Huang
RPMSG needs to share memory with M4, and SCD needs to set this shared memory property accordingly, so the memory region needs to be fixed. Here make CMA range same as its size, so that SCD only sets this region as share property. And also reserve another 4MB for RPMSG. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-16052-1 arm64: imx8qm: refine pcie power on imx8qmRichard Zhu
- Refine the pd definitions of the imx8qm/qxp hsio. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-13951-2 arm64: dts: fsl-imx8qm: enable SAI6, SAI7 and AMIXViorel Suman
Enable SAI6, SAI7 and AMIX nodes. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-02-12MLK-15343-1 ARM: imx: enable pcieb on imx8qmRichard Zhu
Based on base board, enable pcieb lane1, enlarge the CFG mapping space. HSIO configuration is 1 lane PCIEA, 1 lane PCIEB and SATA. PHY configurations: PHY_X2_0 <------> PCIEA 1 lane PHY_X2_1 <------> PCIEB 1 lane PHY_X1 <------> SATA Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-16029 arm64: dts: imx8qm: enable mipi_dsi0 i2c0Gao Pan
add device node to enable mipi_dsi0 i2c0 Signed-off-by: Gao Pan <pandy.gao@nxp.com>
2019-02-12MLK-16027 arm64: dts: imx8qm: correct mipi0 power domainGao Pan
correct mipi0 power domain Signed-off-by: Gao Pan <pandy.gao@nxp.com>
2019-02-12MLK-16023-05 arm64: dts: imx8qm/qxp: enable enet MAC delayed clocksFugang Duan
Since i.MX8QM/QXP ENET version add new feature that support delayed clock for rxc/txc, then enable the feature on imx8qm/qxp arm2 boards. Only enable i.MX8QM/QXP ARM2 board port0 delayed clock, port1 still use PHY delayed clock. i.MX8QXP MEK board also use PHY delayed clock, once get board then enable the port1 and verify MAC delayed clock in MEK board. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2019-02-12MLK-16015-3 arm64: fsl-imx8qm.dtsi: Add ldb aliasesLiu Ying
This patch adds ldb aliases so that the relevant driver is able to distinguish between the two LDB instances. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2019-02-12MLK-15991 arm64: dts: imx8qm: add mlb supportGao Pan
add mlb support for imx8qm Signed-off-by: Gao Pan <pandy.gao@nxp.com>
2019-02-12MLK-15960-6: ARM64: dts: add power domain for audio clocksShengjiu Wang
The mclk_out clock is used as codec's mclk, so need to add its power domain to codec node. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
2019-02-12MLK-15949-3 ARM64: dts: fsl-imx8qm: correct USDHC per clock rateHaibo Chen
Set USDHC2/3 per clock's parent clock to 200MHz. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2019-02-12MLK-15935-01 ARM64: dts: update the critical trip point temp for 8qm/qxpBai Ping
Update the default critical trip point temp to 127C to align with the SCFW's panic alarm temp. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-15927-2: ARM64: dts: iMX8QM and iMX8QXP use specific SAI compatibility ↵Mihai Serban
string For iMX8QM and iMX8QXP the SAI device driver must to add a constraint on the period size because of EDMA requirements. Signed-off-by: Mihai Serban <mihai.serban@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-02-12MLK-15933 arm64: dts: freescale: imx8qm: update A72 cpu freq tableAnson Huang
i.MX8QM SCFW fixes the HP PLL rate calculation, A72 cluster CPU frequency has been changed from 1584MHz to 1596MHz, change the CPU OPP table accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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