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2019-02-22MLK-20940-5 ARM64: dts: Add virtual i2c driver support for 8QXP/QMClark Wang
Add new dts and dtsi file for virtual i2c driver on i.MX8QXP and i.MX8QM board. Merge fsl-imx8qm/8qxp-mek-m4.dts to fsl-imx8qm/8qxp-mek-rpmsg.dtsi. So delete these two files. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
2019-02-12MLK-20797-2: VPU Encoder: reserve memory for actframeming_qian
the region of CMA associated with M0+ core is in [256M, 1G] It can't be guaranteed that it's uncachable for M0+ core. There are some risk, reserve memory to make sure it's in [128M, 256M]. Eliminate the potential risks Signed-off-by: ming_qian <ming.qian@nxp.com>
2019-02-12MLK-20699: VPU Encoder: don't use core number to determine platform typeming_qian
at present, driver use core number(core_type) to determine platform type, 1 means qxp, 2 means qm. this method is not accurate. it's hard to expansion. so get platform type from device id instead of core number. remove core_type in dts. Signed-off-by: ming_qian <ming.qian@nxp.com>
2019-02-12MLK-20637-1 arm64: dts: reserve per dev dma pool for imx rpmsgRichard Zhu
- reserve per dev dma pool for imx rpmsg - move imx8 rpmsg dts node to the -m4 dts files. - re-allocate the vpu rpc reserved memory on qm mek domu dts. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Acked-by: Fugang Duan <fugang.duan@nxp.com>
2019-02-12MLK-20673 ARM64: dts: freescale: imx8qm: disable cpu-idleAnson Huang
Since some ATF versions could have cpu-idle with cpu/cluster power off support enabled, but due to some drivers are NOT ready to support cpu/cluster power off when idle, so i.MX8QM's cpu-idle with cpu/cluster power off is NOT ready at all, disable it to avoid confusion, and ATF can have the full cpu-idle support there. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-02-12MLK-20659: VPU Encoder: refine code to reduce some hard codeming_qian
Encoder driver use macro to define some register absolute address. move the definition to dts, and use relative addresses to define registers more clearly. export these register definition through sysfs. Signed-off-by: ming_qian <ming.qian@nxp.com>
2019-02-12MLK-20633 VPU: adjustment of the reserved memory layout on imx8qm/qx forHuang Chaofan
vpu decoder rpc For vpu decoder change from 0x9040_0000 ~ 0x905F_FFFF to 0x9200_0000 ~ 0x921F_FFFF Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
2019-02-12MLK-20619: VPU Encoder: adjust reserved memory region of encoder rpcming_qian
to reduce the memory hole of the reserved memory layout, adjust reserved memory region of vpu encoder rpc from 0x9060_0000 ~ 0x907F_FFFF to 0x9220_0000 ~ 0x923F_FFFF Signed-off-by: ming_qian <ming.qian@nxp.com>
2019-02-12MLK-20476:VPU Encoder:define max resolution and framerate in dtsming_qian
Signed-off-by: ming_qian <ming.qian@nxp.com>
2019-02-12MLK-20350 VPU: Reduce RPC size and remove decoder_str in dtsHuang Chaofan
Reduce RPC size and remove decoder_str in dts for vpu decoder Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
2019-02-12MLK-20275:VPU Encoder:set proper rpc sizeming_qian
boot-region: 2M per core rpc-buf-size: 512K per core print-buf-size: 512K per core Signed-off-by: ming_qian <ming.qian@nxp.com>
2019-02-12MLK-20174:VPU Encoder:add DebugBufferDesc in RPC interfaceming_qian
fix some typo Signed-off-by: ming_qian <ming.qian@nxp.com>
2019-02-12MLK-20143:VPU Encoder:support suspend of devices modeming_qian
Signed-off-by: ming_qian <ming.qian@nxp.com>
2019-02-12MLK-20128:VPU Encoder:fix rpc memory may overlay for qmming_qian
Signed-off-by: ming_qian <ming.qian@nxp.com>
2019-02-12MLK-20149 VPU: Adjust suspend and resume strategy for vpu decoderHuang Chaofan
Adjust suspend and resume strategy for vpu decoder to handle different cases Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
2019-02-12MLK-19692-2 can: flexcan: dts: add wakeup support for MX8Joakim Zhang
This patch is to add CAN device into ALIASES list due to i.MX8 series would analyze wakeup function from firmware(SCU). Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Andy Duan <fugang.duan@nxp.com> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
2019-02-12MLK-19774 VPU: Add CSR address in dts and remove some CM4 legacy codeHuang Chaofan
Clean vpu decoder code, add CSR address in dts and remove some CM4 legacy code Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
2019-02-12MLK-19688-5:VPU encoder:fix typoming_qian
Signed-off-by: ming_qian <ming.qian@nxp.com>
2019-02-12MLK-19688-3: refactor and cleanup vpu encoder driverming_qian
1.move the definition of reg fw base to dts 2.rm unused vpu clock setting Signed-off-by: ming_qian <ming.qian@nxp.com>
2019-02-12MLK-19381 ARM64: dts: freescale: imx8qm: increase CMA sizeAnson Huang
Increase i.MX8QM CMA size to 960MB to meet 4K video requirement. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-19338 ARM64: dts: freescale: imx8qm: move mu interrupt controller to gicAnson Huang
To support lowest power mode for suspend, if no wakeup source from non-secure partition is enabled, IRQSTEER can be powered off when suspend, so non-secure linux OS needs to pass WU irqchip wakeup source info to ATF, as MU is always enabled as wakeup source, and it is a system level resource, so no need to have it in WU domain. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit d45b2fd47417cc1c4e03616007271e07834cf415)
2019-02-12MLK-19226 VPU: Add support for i.MX8QM B0 vpu decoder and encoderHuang Chaofan
Add support for i.MX8QM B0 vpu decoder and encoder and it is compatiable with i.MX8QXP B0 VPU. Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com> (cherry picked from commit f2d7823da29c55644299eea84a2e866ea188c698)
2019-02-12MLK-17481-2: ARM64: dts: imx8qm: Enable DSPDaniel Baluta
i.mx8QM B0 comes with a DSP (placed in the VPU unit). From the ARM core side DSP local memory (Inst/Data) is mapped at 0x55000000-0x55FFFFFF range. DSP also uses code located in SDRAM mapping starting at 0x92400000. While at it, move rpmsg_node up in order to have all reserved areas sorted by address. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> (cherry picked from commit 1eb4b2ee64c6f1fd7a5d6ceb1f019e876dbdfeb9)
2019-02-12MLK-19065: arm64: dts: imx8qm: sync operating freq with datasheetTeo Hall
Sync operating frequencies for A72 as per latest 8QM datasheet. Signed-off-by: Teo Hall <teo.hall@nxp.com> (cherry picked from commit 1f9b64ca93014852e42d8e34766f003c361e829b)
2019-02-12dts: i.MX8QM/QXP Bring back operating-points for GPU freq scaling.Marius Vlad
Somehow missed when rebaseing to 4.14 Signed-off-by: Marius Vlad <marius-cristian.vlad@nxp.com> Acked-by: Prabhu Sundararaj <prabhu.sundararaj@nxp.com>
2019-02-12MLK-18373 imx8qm: A72 1300mhz is actually 1296mhzLeonard Crestez
Setting a72 clock to 1300mhz and reading back the value from clk reveals the rate is actually 1296mhz: root@imx8mmevk:~# cpufreq-set -c 4 -f 1300000 root@imx8mmevk:~# cat /sys/kernel/debug/clk/clk_summary |grep a72 a72_div 0 0 1296000000 0 0 This causes some cpufreq tests to fail. Fix by setting OPP to 1296000. Fixes: 2b6d66acdd71 ("MLK-18331 ARM64: dts: freescale: imx8qm: update cpufreq set points") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Anson Huang <anson.huang@nxp.com>
2019-02-12MLK-18320 ARM64: dts: imx8qm: align the reserved ddr memoryRichard Zhu
In order to enlarge the CMA easily, change the rpmsg reserved memory region from 0xb800_0000 to 0x9000_0000. And refine the layout of the reserved memory. - RPMSG buffers are allocated from CMA dynamically, and have to be accessed by M4 side. But M4 can only access the 1.5Gbytes DDR memory from 0x8000_0000. So, the finial reserved memory layout is just like the one below. Thus, the largest size of the DDR memory left for CMA, is about 1212Mbytes in theory, since 32Mbytes alignment is required by CMA allocation. reserved-memory layout 0x8800_0000 ~ 0x8FFF_FFFF M4 + RTOS(128M) 0x9000_0000 ~ 0x903F_FFFF RPMSG Vring(4M) 0x9440_0000 ~ 0xDFFF_FFFF(MAX) CMA(1212M)(MAX) Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-18331 ARM64: dts: freescale: imx8qm: update cpufreq set pointsAnson Huang
Update cpufreq set-points according to SCFW changes: A53: add 1104MHz setpoint; A72: add 1300MHz setpoint. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Robin Gong <yibin.gong@nxp.com>
2019-02-12MLK-18224-1 ARM64: dts: freescale: imx8qm: update MU IRQ numberAnson Huang
MU IRQ number is incorrect, update it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-18197: Use MU1 for SCFW API callsTeo Hall
Use correct MU for SCFW API calls to comply with boot container intended usage. Signed-off-by: Teo Hall <teo.hall@nxp.com>
2019-02-12MLK-17907-2 ARM64: dts: imx8qm: add mek xen dtsPeng Fan
To support passthrough, we need some nodes for dom0 and domu. In dom0, the nodes are under root node, however the nodes are under passthrough node for domu. To make consistent, when updating dtsi, to avoid break domu, create a dedicated fsl-imx8qm-device.dtsi only contain device node that might be passthrough to domu. The fsl-imx8qm-device.dtsi contains node previously in fsl-imx8qm.dtsi, no other change. Create a fsl-imx8qm-xen.dtsi to include changes needed for xen. The logic is: fsl-imx8qm.dtsi include fsl-imx8qm-device.dtsi in root node fsl-imx8qm-mek-dom0.dts include fsl-imx8qm-mek.dts fsl-imx8qm-mek-domu.dts include fsl-imx8qm-device.dtsi in passthrough node. In dom0 dts, there is a new node that used by U-Boot to create new software partition, the partition only effects when it has a dedicated MU, there are 5 MUs, 0A is used by Dom0, 1A is used by ATF, so for DomU, 2A/3A/4A could be used: SC_R_MU_0A SC_R_MU_1A SC_R_MU_2A SC_R_MU_3A SC_R_MU_4A. domu { dom2: dom@2 { compatible = "xen,domu"; rsrcs = < .... >; pads = < ... >; }; }; Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-02-12MLK-17908: ARM64: dts: Add power domains for HDMI resourcesSandor Yu
Add power domain PD_HDMI_PLL_0/1 and PD_HDMI_I2S. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2019-02-12MLK-17815-1 dts: arm64: imx8qm: add sata phy regionRichard Zhu
Add the extra imx8qm sata phy register region, and the clock phy_apbclk, mandatory required to access phy registers. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-17799: ARM64: dts: restruct audio power domain treeShengjiu Wang
There is dedicate resource id for audio clocks (PLL_0, PLL_1, AUDIO_CLK_0, AUDIO_CLK_1), the scfw need user to enable the power of resource before using it. The audio clock may used by all audio devices, but the kernel only allow register one power-domains for each device note. So the solution is to add parent-child relationship for them Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-02-12MLK-17698-6 ARM64: dts: freescale: imx8qm: enable mek board pmic thermal zoneAnson Huang
Enable i.MX8QM MEK board PMIC thermal zone. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-17729: ARM64: dts: Add power domains for display resourcesOliver Brown
Some resources are being enabled without the associated resource being powered up. Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2019-02-12MLK-17685-1 Enable CCI perfomance monitorFrank Li
perf list CCI_400_r1/cycles/ [Kernel PMU event] CCI_400_r1/mi_retry_speculative_fetch,source=?/ [Kernel PMU event] CCI_400_r1/mi_rrq_stall_barrier_hazard,source=?/ [Kernel PMU event] CCI_400_r1/mi_rrq_stall_hi_prio_rtq_full,source=?/ [Kernel PMU event] CCI_400_r1/mi_rrq_stall_low_prio_rtq_full,source=?/ [Kernel PMU event] CCI_400_r1/mi_rrq_stall_master_id_hazard,source=?/ [Kernel PMU event] CCI_400_r1/mi_rrq_stall_mid_prio_rtq_full,source=?/ [Kernel PMU event] CCI_400_r1/mi_rrq_stall_qvn_vn0,source=?/ [Kernel PMU event] CCI_400_r1/mi_rrq_stall_qvn_vn1,source=?/ [Kernel PMU event] CCI_400_r1/mi_rrq_stall_qvn_vn2,source=?/ [Kernel PMU event] CCI_400_r1/mi_rrq_stall_qvn_vn3,source=?/ [Kernel PMU event] Signed-off-by: Frank Li <Frank.Li@nxp.com>
2019-02-12MLK-17639-2: ARM64: dts: enable spdif rx for HDMI ARCShengjiu Wang
enable spdif rx for HDMI ARC Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-02-12MLK-17597: Add GICC, GICH, GICV addresses to iMX8QM device tree.Nitin Garg
Adding GICC, GICH, GICV addresses for iMX8QM Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2019-02-12MLK-17552-1 arm: dts: add the dma int for imx pcie epRichard Zhu
Add the dma int for the the imx pcie ep mode for the controllers that has the dma capability. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-17438 arm64: dts: add emvsim0 device node in register address orderGao Pan
Add emvsim0 device node in register address order Signed-off-by: Gao Pan <pandy.gao@nxp.com> Acked-by: Fugang Duan <fugang.duan@nxp.com>
2019-02-12MLK-17319-2 arm64: dts: add emvsim0 device node for imx8qm-mekGao Pan
add emvsim0 device node for imx8qm-mek to support EMVSIM Signed-off-by: Gao Pan <pandy.gao@nxp.com> Reviewed-by: Andy Duan <fugang.duan@nxp.com>
2019-02-12MLK-17341-6: dts: update mipi csi i2c power domain nameSandor Yu
Update mipi csi i2c power domain name. Acked-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2019-02-12MLK-17341-2: dts: Add mipi csi gpio proprietySandor Yu
Add mipi csi0/csi1 GPIO propriety. Add pinctrl setting for mipi_csi0/1 GPIO. Add power up pin for max9286. Acked-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2019-02-12MLK-16715-8 ARM64: dts: fsl-imx8qm: add USB HSIC supportPeter Chen
Add USB HSIC controller support. Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-16715-3 ARM64: dts: fsl-imx8qm: change USB2 controller propertiesPeter Chen
The imx8qm's non-core register controller is more like imx7ulp than imx7d, since imx7d uses Samsung PHY, but imx7ulp and imx8qm use freescale PHY, so imx8qm uses the same compatible for imx7ulp. But imx8qm and imx7ulp's platform are so many differences, so the compatible for driver are different. Besides, we add performance tuning parameters and delete properties which is dedicated for imx7d. Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-17138: arm64: dts: sl-imx8qm.dtsi: Quad display support for 8QMRobert Chiras
Add DTS files fo quad display on 8QM boards. Currently, there is only one file for this: fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dts, which is the combination for 2 LVDS + 2 MIPI-HDMI on LPDDR4 board. This patch adds the other possible use-cases: - 2 LVDS + 2 MIPI-Panel on LPDDR4 - 2 LVDS + 2 MIPI-HDMI on MEK - 2 LVDS + 2 MIPI-Panel on MEK Also: - fix the fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dts, since it contained the old mipi_dsi nodes. - fix the order of mipi_dsi nodes in fsl-imx8qm.dtsi, since this order affects the suspend/resume routines. Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
2019-02-12MLK-15110-7 arm64: dtsi: fsl-imx8qm: Add DPR and PRG supportLiu Ying
This patch adds DPR and PRG support. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2019-02-12MLK-15110-6 arm64: dtsi: fsl-imx8qm: Add DPR0/1/2/3 irq resources for DPU0/1Liu Ying
The Display Prefetch Resolve(DPR) engine is the prefetch engine of DPU. This patch adds the DPR0/1/2/3's irq resources for DPU0/1. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2019-02-12MLK-17126-5: arm64 dts: Move hdmi compatible srtingSandor Yu
Move imx8qm hdmi/dp compatible srting from soc specific dts to board specific dts. BuildInfo: - SCFW e0362348, IMX-MKIMAGE 9841373a, ATF e173337 - U-Boot 2017.03-imx_v2017.03+g3535868 Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
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