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2019-02-12MLK-20224 ARM64: dts: freescale: imx8qxp: disable cpu-idle by defaultAnson Huang
With cpu-idle enabled, we observe that DSI panel display is NOT working on i.MX8QXP MEK board, still under debugging, since cpu-idle ONLY saves ~15mA in runtime, it is NOT valuable enough compare to whole system, so disable it for now until everything is stable enough. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Nitin Garg <nitin.garg@nxp.com>
2019-02-12MLK-19947-3 ARM64: dts: freescale: imx8qxp: add cpu-idle supportAnson Huang
This patch adds cpu-idle support for i.MX8QXP, since different platforms have different cpu-idle latency value, so move the cpu-idle node to platform dtsi. Add GPT as platform broadcast timer, its clock and power are managed in TF-A. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-18089: Add support for DXP/DXTeo Hall
Add dtsi and board configurations for DXP/DX 8QXP derivatives. Separate out the arm2 board individual details for transparency of board and device specifics. Signed-off-by: Teo Hall <teo.hall@nxp.com>
2019-02-12MLK-17305 [MX8QXP-MEK] VPU: "couldn't set vpu_dec_clk clk rate toHuang Chaofan
600000000 (-22)" and "clk: couldn't set vpu_enc_clk clk rate to 600000000 (-22), current rate: 0" when boot up. 100% vpu clock is not settable, remove the assigned-clock-rates from the dts Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
2019-02-12MLK-18483-03 ARM64: dts: imx8qm/qxp: add enet sleep mode supportAndy Duan
Add enet sleep mode support for imx8qm/qxp platforms. Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2019-02-12MLK-18323-3 ARM64: dts: imx8qxp: add adc nodeHaibo Chen
imx8qxp contain one adc, so add adc0 node for imx8qxp. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2019-02-12MLK-18279: ASoC: fsl_dsp: get the information of reserved memory from dtsWeiguang Kong
The reserved memory for dsp is defined in dts file, however, the dsp driver has also defined the address and size of this reserved memory, which is repeated and inflexible. So by cancelling the definition in dsp driver and use system API to get the information of reserved memory from dts dynamically to fix this problem. Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
2019-02-12MLK-18239 ARM64: dts: imx8qxp: change the rpmsg reserved memory regionRichard Zhu
In order to enlarge the CMA easily, change the rpmsg reserved memory region from 0xb800_0000 to 0x9000_0000. And refine the layout of the reserved memory. - RPMSG buffers are allocated from CMA dynamically, and have to be accessed by M4 side. But M4 can only access the 1.5Gbytes DDR memory from 0x8000_0000. So, the finial reserved memory layout is just like the one below. Thus, the largest size of the DDR memory left for CMA, is about 1212Mbytes in theory, since 32Mbytes alignment is required by CMA allocation. reserved-memory layout 0x8000_0000 ~ 0x83FF_FFFF A core + Linux Kernel(64M) 0x8400_0000 ~ 0x85FF_FFFF VPU encoder boot(32M) 0x8600_0000 ~ 0x87FF_FFFF VPU decoder boot(32M) 0x8800_0000 ~ 0x8FFF_FFFF M4 + RTOS(128M) 0x9000_0000 ~ 0x903F_FFFF RPMSG Vring(4M) 0x9040_0000 ~ 0x913F_FFFF VPU decoder rpc(16M) 0x9140_0000 ~ 0x923F_FFFF VPU encoder rpc(16M) 0x9240_0000 ~ 0x943F_FFFF DSP(32M) 0x9440_0000 ~ 0xDFFF_FFFF(MAX) CMA(1212M)(MAX) Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-18245: ARM64: dts: Fix asrc clock sourceShengjiu Wang
Fixes: 7e05dcf668fc ("MLK-16839-2: ARM64: dts: add clock source for asrc") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2019-02-12MLK-18220-5 dts:imx8qxp Remove all clock references from GPIO device entries.Ranjani Vaidyanathan
Controlling GPIO clocks in iMX8 is dependent on power domain, and an unused GPIO's power domain is disabled during startup. This makes it difficult for the GPIO driver to manage clocks for such GPIOs. This causes failures during system suspend/resume when GPIO registers are saved/restored. These LPCG clocks will be always be in an enabled state, similar to earlier iMX processors. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2019-02-12MLK-18250 VPU: Add MU for vpu encoder and decoder power in dts forHuang Chaofan
scfw xrdc enforcing, and add sync for v4l2 driver and firmware Add MU for vpu encoder and decoder power in dts for scfw xrdc enforcing, and add sync for v4l2 driver and firmware Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
2019-02-12MLK-18245-2: ARM64: dts: refine the power domain tree for audio devicesShengjiu Wang
In the latest scfw design, the power domain of device should be explicit enabled in kernel, otherwise there will be kernel dump. For example, when using audio device to playback, the DMA channel's power domain should be eanbled, but to avoid to call scfw API in driver, we need to refine the tree of power domain, define the DMA channel's power domain as audio device's parent. And same requirement for DSP, the MU and DSP_RAM is required by DSP driver. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-02-12MLK-18241-2: ARM64: dts: freescale: imx8qxp: add edma channel power domain ↵Robin Gong
for LPUART Add edma channel power domain for LPUART to make sure the specific edma channel power up in dma mode. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
2019-02-12MLK-18241-1 ARM64: dts: freescale: imx8qxp: correct edma indexRobin Gong
Correct edma index for imx8qxp to mach the right rsrc id of scfw. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
2019-02-12MLK-18237-3 XRDC: JPEG ENC/DEC fix crash missed power resourceFrank Li
[ 5.184399] Unhandled fault: synchronous external abort (0x96000210) at 0xffff00000b000000 [ 5.184824] (null): mxc_isi_capture_open, No remote pad found! [ 5.187470] (null): mxc_isi_capture_open, No remote pad found! [ 5.192734] (null): mxc_isi_capture_open, No remote pad found! [ 5.199931] (null): mxc_isi_capture_open, No remote pad found! [ 5.219447] Internal error: : 96000210 [#1] PREEMPT SMP [ 5.224681] Modules linked in: [ 5.227755] CPU: 2 PID: 3028 Comm: v4l_id Not tainted 4.9.88-04903-ga209cd8 #464 [ 5.235162] Hardware name: Freescale i.MX8QXP MEK (DT) [ 5.240305] task: ffff80083411cb00 task.stack: ffff80083b7ac000 [ 5.246254] PC is at clk_gate2_scu_enable+0x3c/0xa8 Signed-off-by: Frank Li <Frank.Li@nxp.com>
2019-02-12MLK-18237-2 XRDC: DSP: add mu power resource to avoid crashFrank Li
[ 2.300213] Unhandled fault: synchronous external abort (0x96000210) at 0xffff000014dd0000 [ 2.308584] Internal error: : 96000210 [#1] PREEMPT SMP [ 2.313813] Modules linked in: [ 2.316875] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.88-04903-ga209cd8 #464 [ 2.324271] Hardware name: Freescale i.MX8QXP MEK (DT) [ 2.329407] task: ffff80083a088000 task.stack: ffff80083a034000 [ 2.335329] PC is at MU_Init+0x0/0x38 [ 2.338994] LR is at dsp_mu_init+0xb8/0x140 Signed-off-by: Frank Li <Frank.Li@nxp.com>
2019-02-12MLK-18237 XRDC: rpmsg: add power domain to avoid crashFrank Li
[ 0.737561] Unhandled fault: synchronous external abort (0x96000210) at 0xffff00000c160000 [ 0.745503] Internal error: : 96000210 [#1] PREEMPT SMP [ 0.750695] Modules linked in: [ 0.753739] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.88-04903-ga209cd8 #464 [ 0.761118] Hardware name: Freescale i.MX8QXP MEK (DT) [ 0.766246] task: ffff80083a088000 task.stack: ffff80083a034000 [ 0.772160] PC is at MU_Init+0x0/0x38 [ 0.775805] LR is at imx_rpmsg_probe+0x22c/0x510 Signed-off-by: Frank Li <Frank.Li@nxp.com>
2019-02-12MLK-18224-2 ARM64: dts: freescale: imx8qxp: update MU IRQ numberAnson Huang
MU IRQ number is incorrect, update it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-18220-2 XRDC:Fix power domain and clock entries in DTSRanjani Vaidyanathan
Ensure that every resource is associated with a power domain and clocks required. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2019-02-12MLK-18198: Add pd domain to GPIO device tree nodesTeo Hall
Add power domain information to GPIO nodes for correct power up sequence. Signed-off-by: Teo Hall <teo.hall@nxp.com>
2019-02-12MLK-18197: Use MU1 for SCFW API callsTeo Hall
Use correct MU for SCFW API calls to comply with boot container intended usage. Signed-off-by: Teo Hall <teo.hall@nxp.com>
2019-02-12MLK-17747: dsp: use the name of dsp instead of hifiWeiguang Kong
In order to avoid the name problem going forward with integration with Qcom, Qcom has their own dsp and hifi is competitor, so the hifi name should not be used in our code. So use the name of dsp instead of hifi to fix this problem. Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
2019-02-12MLK-18101-2 arm64: dtsi: fsl-imx8qxp: Add prg1 for dpr1_channel2Yuchou Gan
On QXP B0 board, prg1 can alternative connect to dpr_channel1 and channel2. And if enable PRG0_SEL:BLIT0, prg1 will connect to channel2, so it could support 2-plane format tile to linear convert. Signed-off-by: yuchou gan <yuchou.gan@nxp.com>
2019-02-12MLK-18003 ARM64: dts: imx8qxp: change back usdhc clock parent to PLL0Haibo Chen
8QXP B0 chip already fix the PLL0 unstable issue, so change back the usdhc clock parent to PLL0. To track the history, refer to commit 7834eee6dfa8 ("MLK-17188-2 ARM64: dts: imx8qxp: assign usdhc clock parent"). Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2019-02-12MLK-17800-3: ARM64: dts: Correct gpt interrupt numberShengjiu Wang
The workaround is using dma general interrupt for gpt for gpt own interrupt share same interrupt number with dma interrupt. Remove the workaround, then correct this setting. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2019-02-12MLK-17933[IMX8QXP B0] Change compatible name for B0 encoder and decodernxa13443
Change compatible name for B0 encoder and decoder in fsl-imx8qxp.dtsi Signed-off-by: nxa13443 <chaofan.huang@nxp.com>
2019-02-12MLK-17902 [IMX8QXP B0]VPU ENCODER and DECODER on IMX8QXP B0 boardnxa13443
Add vpu decoder and encoder for imx8qxp b0 board, decoder can support H265 H264 MPEG2 MPEG4 H263 etc encoder can support H264 Signed-off-by: nxa13443 <chaofan.huang@nxp.com>
2019-02-12MLK-17790-1: dts: add clocks for CI_PI subsystmeGuoniu.Zhou
Because QXP will drop parent clock info of CI_PI SS after system suspend/resume, so driver need to record the relationship of clocks. Reviewed-by: sandor.yu <sandor.yu@nxp.com> Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com> (cherry picked from commit d4b94c2b128850bed8ec4c00ce0c0e3f86a05fcd)
2019-02-12MLK-17230-3: CI_PI: add device nodes for CI_PI SSGuoniu.Zhou
Add clock and power domain device nodes for CI_PI subsystem. Reviewed-by: Sandor.Yu <sandor.yu@nxp.com> Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com> (cherry picked from commit 825392c25d2f3d430a877fc34e5268a4bd0324f0)
2019-02-12MLK-17799: ARM64: dts: restruct audio power domain treeShengjiu Wang
There is dedicate resource id for audio clocks (PLL_0, PLL_1, AUDIO_CLK_0, AUDIO_CLK_1), the scfw need user to enable the power of resource before using it. The audio clock may used by all audio devices, but the kernel only allow register one power-domains for each device note. So the solution is to add parent-child relationship for them Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-02-12MGS-3724 increase the core clock rate for qxp B0 board.Yuchou Gan
The qxp B0 board gpu core clock rate is 700MHz, increase to it. Signed-off-by: Yuchou Gan<yuchou.gan@nxp.com>
2019-02-12MLK-17698-4 ARM64: dts: freescale: imx8qxp: enable mek board pmic thermal zoneAnson Huang
Enable i.MX8QXP MEK board PMIC thermal zone. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-17698-2 ARM64: dts: freescale: imx8qxp: update thermal zone infoAnson Huang
Update thermal zone number, including CPU thermal zone and DRC thermal zone. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-17729: ARM64: dts: Add power domains for display resourcesOliver Brown
Some resources are being enabled without the associated resource being powered up. Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2019-02-12MLK-17561-2 ARM64:dts: Update to the latest SCFW API based on commit 97b8a6eeRanjani Vaidyanathan
commit 97b8a6eed4eee19ec8a60dedfffc2f5f3d8933c5 Author: Chuck Cannon <chuck.cannon@freescale.com> Date: Tue Feb 6 08:54:16 2018 -0600 Add unique ID API call. Required to get info needed for SECO fuse programming. Added info command to DM. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2019-02-12MLK-17552-1 arm: dts: add the dma int for imx pcie epRichard Zhu
Add the dma int for the the imx pcie ep mode for the controllers that has the dma capability. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-17341-6: dts: update mipi csi i2c power domain nameSandor Yu
Update mipi csi i2c power domain name. Acked-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2019-02-12MLK-17290-06 arm64: dts: gpio: add mipi csi SS gpio clock and power domainFugang Duan
GPIO in MIPI CSI SS also has its related ipg clock and power domain, add them. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Tested-by: Guoniu.Zhou <guoniu.zhou@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com>
2019-02-12MLK-17188-2 ARM64: dts: imx8qxp: assign usdhc clock parentAnson Huang
Assign i.MX8QXP uSDHC clocks parent to from PLL1. This is a workaround for i.MX8QXP usdhc, PLL0 of CONN SS is not stable sometimes, root cause is still under investigation in design team. Now change to source from PLL1. Due to PLL1 is 1000MHz, so EMMC HS400ES mode can only work at 166MHz, compare to the former 198MHz, the performance has small drop, read performance drop about 10%, write performance drop about 6%. SD do not has this side effect. When PLL0 unstable issue is fixed, will change back to use PLL0. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> Tested-by: Haibo Chen <haibo.chen@nxp.com>
2019-02-12MLK-16715-10 ARM64: dts: fsl-imx8qxp: change properties for USB2Peter Chen
The changes include: compatible, performance tuning parameters, and delete the property which is dedicated to imx7d. Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-16549-1: mipi_csi: fix camera sensor i2c R/W issueGuoniu.Zhou
Because there is a level shifter between mipi csi controller and max9286 camera sensor bridge. We need configure RESET_B and ENABLE pins as GPIO, otherwise the bridge will not work normally. Reviewed-by: Sandor.Yu <sandor.yu@nxp.com> Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
2019-02-12MLK-15110-12 arm64: dtsi: fsl-imx8qxp: Add DPR and PRG supportLiu Ying
This patch adds DPR and PRG support. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2019-02-12MLK-15110-11 arm64: dtsi: fsl-imx8qxp: Add DPR0/1 irq resources for DPULiu Ying
The Display Prefetch Resolve(DPR) engine is the prefetch engine of DPU. This patch adds the DPR0/1's irq resources for DPU. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2019-02-12MLK-16976-6 ARM64: dts: fsl-imx8qxp: let USB have wakeup capabilityPeter Chen
Let PM code know USB has wake system up capability. BuildInfo: - SCFW 245582b, IMX-MKIMAGE 0ad6069a, ATF 6bd98a3 - U-Boot 2017.03-imx_v2017.03+gfa65b0a Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-16976-1 ARM64: dts: fsl-imx8: add OTG register regions for Cadence USB3Peter Chen
Add OTG register regions for Cadence USB3. BuildInfo: - SCFW 245582b, IMX-MKIMAGE 0ad6069a, ATF 6bd98a3 - U-Boot 2017.03-imx_v2017.03+gfa65b0a Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-17120: arm64: dts: assign the clock rate for GPMI NAND in DTHan Xu
Assign the clock rate for GPMI NAND on i.MX8QXP ARM2 device tree. To keep the same clock rate after system suspend/resume, we need to set assign a clock rate for GPMI NAND, otherwise the timing register won't match with the clock setting. The code change also a workaround for SCU clock rate setting. NAND use a very low clock freq (22Mhz) and safe timing to identify which chips were connected. This low freq divide from high freq parent clock(1Ghz) caused the SCU clock divider go beyond the limit (31) SCU need to implement the clk_round_rate to found this issue and return error value to upper layer. Right now assign 50Mhz for GPMI initial clock as a workaround. Signed-off-by: Han Xu <han.xu@nxp.com>
2019-02-12MLK-17072-2: ARM64: dts: freescale: imx8qm/qxp: enable MU as wakeup sourceRobin Gong
Enable MU as wakeup source in dts. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
2019-02-12MLK-16938 ARM64: dts: imx8: refine the imx8 dtsRichard Zhu
- Add the clk_req property for imx8 pcie, make sure that the clk_req would be active. - Correct the spell mistake of pcie pinctrl on imx8qxp. - Fix the potential conflication with the usage of SC MU, remove the useless "fsl,imx8-mu" of rpmsg. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-16918-10: arm64: dtsi: fsl-imx8qxp: Update dtsi for nwl-mipi-dsiRobert Chiras
Now, the NWL MIPI-DSI driver is implemented as a real bridge and uses the "nwl,mipi-dsi" compatible. This patch updates the mipi-dsi nodes to comply with the new design of NWL and NWL_IMX drivers. Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
2019-02-12MLK-16818-1 ARM64: dts: imx8: modify the dts to enable ep rc supportRichard Zhu
- Correct the comments of iMX8QM PCIEB - Enlarge the CFG space of iMX8QXP PCIEB. - PCIE port maybe hard-wired in the hardware design. Use the hard-wired property to specify it on iMX8MQ. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
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