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Use generic node name and specific label name.
Add m25p,fast-read.
Use dt-bindings constants in interrupts instead of using numbers.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
(cherry picked from commit 58f10e679079d68275f961f131bb146abf532b6d)
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Update rx and tx bus-width to 1.
Use compatibles as "jedec,spi-nor" to probe flash without displaying warning:
found s25fs512s, expected m25p80
Remove property 'big-endian' as it is not used by new driver anymore.
Also, update dtsi compatibles to use "fsl,ls1021a-qspi".
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
(cherry picked from commit e9f44d4f413bc6b8cd0d9fdaece2bcc1cb1edbc5)
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To keep platform specific properties in the platform dts files,
remove pfe_mac nodes from dtsi and define them in dts files.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
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gemac-bus-id is unused property and is removed.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
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Replace properties "fsl,gemac-phy-id" and "fsl,pfe-phy-if-flags"
and use phy-handle instead.
Create mdio node with phy-handles defining PHYs available on the
mdio bus.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
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commit 65c558ec270003e8e99cb58c940d3b913d08fa39
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Tue May 15 08:47:19 2018 +0800
arm64: dts: ls1012a: correct the register range of dcfg
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 8f7b4cded4ea1fca53516ae8f5d5bc89af291f26
Author: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Date: Mon May 7 11:52:04 2018 +0530
arm64: dts: ls1012a: Add LS1012A-FRWY board support
LS1012A-FRWY is a different design from LS1012A-FRDM,
but has some common SoC features. Key feature on this
board is 2x1G SGMII PFE MAC, Micro SD, USB 3.0, DDR,
QuadSPI, Audio, UART.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
commit 94fc77837b3b6f4213a49b29ddc3e09e38ae5fbb
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Mon Apr 2 16:16:47 2018 +0800
arm64: dts: ls1012a: add dts entry for A-010650
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit d4164a6d8cffd8f09c451073754834d58b7ace19
Author: Suresh Gupta <suresh.gupta@nxp.com>
Date: Thu Feb 1 23:44:15 2018 +0530
arm64: dts: freescale: ls1012a: Add DT nodes for qspi
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
commit 4fdc98a03492b732a48426a4180f7d6a36847e71
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Wed Nov 1 10:31:47 2017 +0800
arm64: dts: ls1012a: correct the i2c clock to 1/4 platform pll
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit bb534725996b92aff853a4dee43738629fd4ac08
Author: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Date: Wed Nov 29 06:31:23 2017 +0530
arm64: dts: freescale: ls1012a: Disable PCIe node as default
Keep PCIe node in "disabled" status as SoC default.
Only enable it for boards with PCIe circuit designed,
such as LS1012ARDB and LS1012AQDS.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
commit 6b9a3244baba2c5126f349800ecaad83ba97ee47
Author: Calvin Johnson <calvin.johnson@nxp.com>
Date: Mon Oct 16 12:25:19 2017 +0530
arm64: dts: freescale: ls1012a: fix RGMII tx delay issue
Recently logic to enable RGMII tx delay was changed by
below patch.
https://patchwork.kernel.org/patch/9447581/
Based on the patch, enabling tx delay again using rgmii-txid.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
commit 1e17e247088f6e2c08041559e38053b70a9d2bbe
Author: Calvin Johnson <calvin.johnson@nxp.com>
Date: Sat Sep 16 14:20:23 2017 +0530
arm64: dts: freescale: ls1012a: update with pppfe support
Update ls1012a dtsi and platform dts files with
support for ppfe.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
commit e9661ed864d2a9d437057f97729410bb9af994f2
Author: Suresh Gupta <suresh.gupta@nxp.com>
Date: Tue May 16 17:17:21 2017 +0530
arm64: dts: ls1012a: add the DTS node for QSPI support
There is a s25fs512s qspi flash on QDS, RDB and FRDM board.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
commit ed9c51239461fe0322da2e93f50033ea0d05bc4f
Author: Chenhui Zhao <chenhui.zhao@nxp.com>
Date: Fri May 5 17:45:15 2017 +0800
arm64: dts: ls1012a: add ftm0 node
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Replace license text with corresponding SPDX identifiers and update the
format of existing SPDX identifiers to follow the new guideline
Documentation/process/license-rules.rst.
Note that some of the files mentioned X11 license previously but the
license text actually matches MIT license.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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There are two eSDHC controllers in LS1012A. This patch is to add
eSDHC nodes for ls1012a dts. Also enable eSDHC for RDB/QDS boards.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Update the copyright claims to comply with company policy.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Updated sata node to add ecc register address and dma coherence
property.
Enable sata on ls1012a platforms as well.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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LS1012A features an advanced 64-bit ARM v8 CortexA53 processor
with 32 KB of parity protected L1-I cache, 32 KB of ECC protected
L1-D cache, as well as 256 KB of ECC protected L2 cache.
Features summary
One 64-bit ARM-v8 Cortex-A53 core with the following capabilities
- Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC
protection
- Speed up to 800 MHz
- Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache
- Neon SIMD engine
- ARM v8 cryptography extensions
One 16-bit DDR3L SDRAM memory controller
ARM core-link CCI-400 cache coherent interconnect
Cryptography acceleration (SEC)
One Configurable x3 SerDes
One PCI Express Gen2 controller, supporting x1 operation
One serial ATA (SATA Gen 3.0) controller
One USB 3.0/2.0 controller with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1012A
SoC family:
- fsl-ls1012a.dtsi:
DTS-Include file for FSL LS1012A SoC.
- fsl-ls1012a-frdm.dts:
DTS file for FSL LS1012A FRDM board.
- fsl-ls1012a-qds.dts:
DTS file for FSL LS1012A QDS board.
- fsl-ls1012a-rdb.dts:
DTS file for FSL LS1012A RDB board.
Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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