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Named the ports node of the Felix Eth switch so it can be used in DT
overlays to associate the ports with proper PHYs.
Ports are now by default disabled in dtsi, so if the board dts doesn't
do anything about them they stay disabled.
Updated RDB and QDS dts files to match.
Replaced all 'phy-connection-type' with 'phy-mode'.
The set-up for protocol 7777 on QDS was changed to a single quad port card
in slot 1. This requires a QDS board with no lane B rework and a AQR412
or similar PHY card without any lane rework done on it.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
(cherry picked from commit 0462421755cb92b3ee9ace632d15a9a19db9f14c)
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Use ethernet-phy@ADDR, previously the numbers were wrong.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
(cherry picked from commit 4085dc853441dd17b53a95d19f324d76d946fee3)
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This enables monitoring of link status and AN. It should also physically
enable SGMII AN with the VSC8514 PHY, but in practice that is still
hardcoded as "on" in the PHY driver, at the moment. So since Felix
actually disables SGMII AN when this DT property is absent, this would
result in an in-band AN mismatch between the MAC and the PHY. So this
property is required for the moment for this MAC/PHY combination.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
(cherry picked from commit 57575d3b92a1b2ca9fb0e75dcf20d8283df2dcfd)
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This reverts commit 841edb98671cfc4d6f010393ac429c78082ec4bd.
There are 2 separate issues with interrupts on the LS1028A-RDB board:
1. The GPIO1_DAT25 interrupt line is shared, so there is a real risk of
race conditions if used in edge-triggered mode, as we currently do.
This can be illustrated in the following setup:
- Take 2 LS1028A-RDB boards
- Connect swp0 to swp0, swp1 to swp1, swp2 to swp2
- Plug/unplug the power to board 2, 10 times in a row. This will make
the PHYs lose link simultaneously.
- Notice that at one point, the net devices on board 1 remain in a
state where not all the links are down (visible in "ip link"):
5: swp0: <BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state UP mode DEFAULT group default qlen 1000
link/ether be:97:36:d3:3d:70 brd ff:ff:ff:ff:ff:ff
6: swp1: <BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state UP mode DEFAULT group default qlen 1000
link/ether be:97:36:d3:3d:71 brd ff:ff:ff:ff:ff:ff
7: swp2: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state DOWN mode DEFAULT group default qlen 1000
link/ether be:97:36:d3:3d:72 brd ff:ff:ff:ff:ff:ff
This cannot be solved by making the interrupts level-triggered,
because the gpio-mpc8xxx controller only supports generating
edge-triggered interrupts. So the effective reality is that we
cannot not use shared interrupts connected to the gpio1
interrupt-parent.
2. The uBUS1 and uBUS2 slots that share this interrupt line with the
Ethernet PHYs are not pulled up by default, they are left floating on
current revisions of the LS1028A-RDB boards. So sufficient electrical
noise on these lines will make the CPLD think there's an interrupt
request, so it asserts the GPIO1_DAT25 signal and leaves it asserted.
This means that the PHYs on those boards will never have link when
used in interrupt mode, because their IRQ will be masked by the uBUS
line that is erroneously kept asserted. In poll mode this issue does
not occur.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
(cherry picked from commit f0d8d28ed417194f9e83e495949225d18d1505c7)
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Add DP DT nodes for configure and enable the HD Display
controller on LS1028ARDB and LS1028AQDS boards.
Signed-off-by: Wen He <wen.he_1@nxp.com>
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layerscape otg function should be supported HNP SRP and ADP protocol
accroing to rm doc, but dwc3 code not realize it and use id pin to
detect who is host or device(0 is host 1 is device) this patch is to
enable OTG mode on ls1028ardb ls1088ardb and ls1046ardb in dts
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
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Use the PHY interrupt wired to GPIO pins as part of MDIO WA performance
impact mitigation.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
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This patch is to enable emmc hs400 mode for ls1028ardb
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
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Just link the switch PHY nodes to the central MDIO
controller PCIe endpoint node on ls1028 (implemented
as PF3) so that PHYs are configurable via MDIO.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
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This patch add HDP PHY Controller related nodes on the LS1028ARDB.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Wen He <wen.he_1@nxp.com>
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Add fspi node property for LS1028A SoC for FlexSPI driver.
Property added for the FlexSPI controller and for the connected
slave device for the LS1028ARDB and LS1028AQDS target.
This is having one SPI-NOR flash device, mt35xu02g connected at
CS0.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
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Add flexcan node in LS1028A SOC file as well as in QDS and RDB files.
The device tree bindings used can be referred from
Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
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This patch is to add esdhc node and enable SD UHS-I,
eMMC HS200 for ls1028ardb/ls1028aqds board.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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LS1028A has a SEC v5.0 compatible security engine.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add nxp sa56004 chip node for temperature monitor.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Change the sata node to enable sata.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This patch adds Audio DT nodes for LS1028ARDB and LS1028AQDS boards.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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RDB board
The LS1028A RDB board features an Atheros PHY connected over
SGMII to the ENETC PF0 (or Port0). ENETC Port1 (PF1) has no
external connection on this board, so it can be disabled for now.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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LS1028A contains two ARM v8 CortexA72 processor cores
with 32 KB L1-D cache and 48 KB L1-I cache
Features summary
Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs
- Arranged as single clusters of two cores sharing a 1 MB L2 cache
- Speed Up to 1.3 GHz
- Support for cluster power-gating.
Cache coherent interconnect (CCI-400)
- Hardware-managed data coherency
- Up to 400 MHz
32-bit DDR4 SDRAM memory controller with ECC
Two PCIe 3.0 controllers
One serial ATA (SATA 3.0) controller
Two high-speed USB 3.0 controllers with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1028A
SoC family:
- fsl-ls1028a.dtsi:
DTS-Include file for NXP LS1028A SoC.
- fsl-ls1028a-qds.dts:
DTS file for NXP LS1028A QDS board.
- fsl-ls1028a-rdb.dts:
DTS file for NXP LS1028A RDB board
Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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