Age | Commit message (Collapse) | Author |
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Ls208xa has several thermal sensors. Add all the sensor id to dts
to enable them.
To make the dts cleaner, re-organize the nodes to split out the
common part so that it can be shared with other SoCs.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
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commit 46123df3a174f0d76c8b954a0386e64841453836
Author: Florinel Iordache <florinel.iordache@nxp.com>
Date: Thu Aug 9 12:29:18 2018 +0300
arm64: dts: updates for Unified Backplane driver
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
commit 76a741dbb9b93ea9ab2f6122b8df5bc4f0db7676
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Sat Apr 28 00:20:16 2018 +0530
arm64: dts: ls208x: add dma-cohernet property in fsl-mc node
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
commit f6309e9dc8e0c6171a43fd6759123b5de1c574aa
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Mon Apr 2 16:27:23 2018 +0800
arm64: dts: ls208xa: add dts entry for A-010650
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 8c37bad2038a210a4f0a369fd946aaae4317eac4
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Fri Apr 20 17:14:10 2018 +0530
arm64: dts: ls208x: add dma ranges property
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
commit 38566bbd5ca6747b30d2f0c251bbcfe0723df8c6
Author: Changming Huang <jerry.huang@nxp.com>
Date: Wed Apr 19 12:49:50 2017 +0800
arm/arm64: dts: Add property snps incr burst type adjustment for
INCR burst type for dwc3
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
commit dbb65ea8ee1d46067e756c6d64c7fe66a0058f49
Author: Pankaj Bansal <pankaj.bansal@nxp.com>
Date: Mon Mar 5 12:37:04 2018 +0530
arm64: dts: ls208x: remove NXP Erratum A008585 from LS2088A.
NXP Erratum A008585 affects A57 core cluster used in LS2085rev1.
However this problem has been fixed in A72 core cluster used in
LS2088.
Therefore remove the erratum from LS2088A. Keeping it only in
LS2085.
Cc: <stable@vger.kernel.org> # 4.14
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Sandeep Malik <sandeep.malik@nxp.com>
Acked-by: Priyanka Jain <priyanka.jain@nxp.com>
commit 85f41b0f6abe6b9d7d303790bb3712ed559890e9
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Mon Feb 26 10:39:54 2018 +0530
arm64: dts: ls208xa: add dma coherent property in smmu node
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
commit e910d8b78b823a625451b1da7ae7499dadde2ae9
Author: Suresh Gupta <suresh.gupta@nxp.com>
Date: Thu Feb 1 23:49:56 2018 +0530
arm64: dts: freescale: ls208xa: Modify DT nodes for qspi
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
commit 7654ef78c8c85de3a43dfa0dffd572d589ea1332
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Wed Nov 1 10:34:04 2017 +0800
arm64: dts: ls208xa: correct the i2c clock to 1/2 platform pll
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit efdb129228baa6a999c06072338b979d783d7b60
Author: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Date: Thu Aug 31 14:45:02 2017 +0530
arm64: dts: ls208xa: Add iommu-map property for pci
This patch adds iommu-map property for PCIe, which enables
SMMU for these devices on LS208xA devices.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
commit 45af5d025eafaf4a85000e16e5f47992de663ff6
Author: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
Date: Mon Aug 21 11:46:59 2017 +0300
arm64: dts: ls2088a: update backplane support with dpmac connections
Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
commit b2ede6c088a883fceb348e8659253b2c7cdeeff8
Author: Santan Kumar <santan.kumar@nxp.com>
Date: Thu Jun 22 13:04:00 2017 +0530
arm64: dts: ls2088ardb: Update nodes for QSPI
-As per board design, different QSPI flash is connected on
boards, hence change QSPI flash node from s25fl256s1 to s25fs512ss
in
device tree.
-Enable fast-read support in QSPI node.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
commit d5324a75c56e9f9210113e51cffa846a86b50fbd
Author: Santan Kumar <santan.kumar@nxp.com>
Date: Mon Jun 19 15:26:03 2017 +0530
arm64: dts: ls2081ardb: Update nodes for QSPI, SATA, INA220
Update ls2081ardb.dts for below nodes:
-As per updated board design, different QSPI flash is connected on
boards, hence change QSPI flash node from n25q512a to s25fs512ss
in
device tree.
-Enable dual flash support in QSPI node.
-Add DTS node for INA220.
-Enable SATA node.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Tao Yang <b31903@freescale.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
commit 43d506fa19e1e50e4c2e4f9689ad3c60d9a06d71
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Thu May 11 08:42:19 2017 +0800
arm64: dts: ls208x: add property for PCA954x Mux device
PCA954x Mux device should never be turned-off after power-on. if
device tree contians "i2c-mux-never-disable" property for pca954x
device node, it can ensure that skip disabling PCA954x Mux device.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 6d3a96446a7ffccb0b9936b616d855c8d5572bce
Author: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Date: Wed May 3 14:26:35 2017 +0000
arm64: dts: fsl/ls1088,ls208x: Add mdio and phy nodes
Add mdio and phy nodes for the following FSL platforms:
- LS1088A RDB
- LS2080A QDS & RDB
- LS2088A QDS, RDB & simu
Contains contributions from patches by the following authors:
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava
<pratiyush.srivastava@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
commit 0443625ea24bc4ea315c30b718712254c588bd18
Author: Suresh Gupta <suresh.gupta@nxp.com>
Date: Fri May 5 13:54:22 2017 +0530
arm64: dts: ls208xa: Add QSPI Flash node for RDB
This is temporary patch, will rewrite for open source
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
commit ed0ce1d49aa72d12ea54f82d3771a377c68af37e
Author: Priyanka Jain <priyanka.jain@nxp.com>
Date: Thu Apr 13 16:49:40 2017 +0530
arm64: dts: ls2081ardb: Add DTS support for NXP LS2081ARDB
This patch add support for NXP LS2081ARDB board which has
LS2081A SoC.
LS2081A SoC is 40-pin derivative of LS2088A SoC
So, from functional perspective both are same.
Hence,ls2088a SoC dtsi files are included from ls2081ARDB dts
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
commit e4fb842554a5e7b8c3f6e3c243222dbe4515aee3
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Thu Apr 27 15:01:54 2017 +0800
arm64: dts: ls208xa: add ftm0 nodes
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 64c3e2c3a7ddc89c3c23c012ee364f2c014524d2
Author: costi <constantin.tudor@freescale.com>
Date: Fri Mar 3 18:08:28 2017 +0200
arm64: dts: fsl-ls2088: Add mdio/phy devices
Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
commit 3bcdc4de0a1c9e6f4a4ddc916e8efe8044d8bbfd
Author: Po Liu <po.liu@nxp.com>
Date: Fri Sep 30 17:11:36 2016 +0800
arm64: dts: ls1043/ls2080: add pcie aer/pme interrupt-name property
Some platforms(NXP Layerscape for example) aer/pme interrupts was
not
MSI/MSI-X/INTx but using interrupt line independently. This patch
add "aer", "pme" interrupt-names for aer/pme interrupt.
With the interrupt-names "aer", "pme" code could probe aer/pme
interrupt
line for pcie root port, replace the aer/pme interrupt service irqs.
This is intend to fixup the Layerscape platforms which aer/pmes
interrupts
was not MSI/MSI-X/INTx, but using interrupt line independently.
Since the interrupt-names "intr" never been used. Remove it.
Signed-off-by: Po Liu <po.liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
commit 64d859836d3d194e8bc926bb951fd21859689824
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Mon Dec 5 05:20:51 2016 +0530
arm64: dts: ls208xa: Comply with the new iommu binding for fsl_mc
fsl-mc bus support the new iommu-map property. Comply to this
binding
for fsl_mc bus.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
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The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add such missing properties.
Do minor rearrangement as well to keep ordering consistent.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Replace license text with corresponding SPDX identifiers and update the
format of existing SPDX identifiers to follow the new guideline
Documentation/process/license-rules.rst.
Note that some of the files mentioned X11 license previously but the
license text actually matches MIT license.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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ls208xa supports another cpu idle state which is pw20 which saves
more power when cpu is idle.
It was implemented through psci firmware.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Update the copyright claims to comply with company policy.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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LS2088A and LS2080A are similar SoCs with a few differences like
ARM cores etc.
Reorganize the LS2080A device tree to move the common nodes to:
- fsl-ls208xa.dtsi
- fsl-ls208xa-rdb.dtsi
- fsl-ls208xa-qds.dtsi
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann:
"A couple of interesting new SoC platforms are now supported, these are
the respective DTS sources:
- Samsung Exynos5433 mobile phone platform, including an (almost)
fully supported phone reference board.
- Hisilicon Hip07 server platform and D05 board, the latest iteration
of their product line, now with 64 Cortex-A72 cores across two
sockets.
- Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product
line, used in Android tablets and ultra-cheap development boards
- NXP LS1046A Communication processor, improving on the earlier
LS1043A with faster CPU cores
- Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810)
mobile phone SoCs
- Early support for the Nvidia Tegra Tegra186 SoC
- Amlogic S905D is a minor variant of their existing Android consumer
product line
- Rockchip PX5 automotive platform, a close relative of their popular
rk3368 Android tablet chips
Aside from the respective evaluation platforms for the above chips,
there are only a few consumer devices and boards added this time:
- Huawei Nexus 6P (Angler) mobile phone
- LG Nexus 5x (Bullhead) mobile phone
- Nexbox A1 and A95X Android TV boxes
- Pine64 development board based on Allwinner A64
- Globalscale Marvell ESPRESSOBin community board based on Armada 3700
- Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board
For the existing platforms, we get bug fixes and new peripheral
support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom,
Rockchip, Berlin, and ZTE"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits)
arm64: dts: fix build errors from missing dependencies
ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible
ARM64: dts: meson-gxl: Add support for Nexbox A95X
ARM64: dts: meson-gxm: Add support for the Nexbox A1
ARM: dts: artpec: add pcie support
arm64: dts: berlin4ct-dmp: add missing unit name to /memory node
arm64: dts: berlin4ct-stb: add missing unit name to /memory node
arm64: dts: berlin4ct: add missing unit name to /soc node
arm64: dts: qcom: msm8916: Add ddr support to sdhc1
arm64: dts: exynos: Enable HS400 mode for eMMC for TM2
ARM: dts: Add xo to sdhc clock node on qcom platforms
ARM64: dts: Add support for Meson GXM
dt-bindings: add rockchip RK1108 Evaluation board
arm64: dts: NS2: Add PCI PHYs
arm64: dts: NS2: enable sdio1
arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash
arm64: tegra: Add NVIDIA P2771 board support
arm64: tegra: Enable PSCI on P3310
arm64: tegra: Add NVIDIA P3310 processor module support
arm64: tegra: Add GPIO controllers on Tegra186
...
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Add the dts node for device configuration unit that provides
general purpose configuration and status for the device.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Scott Wood <oss@buserror.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
Freescale arm64 device tree updates for 4.10:
- Enable Thermal Monitoring Unit (TMU) for thermal management on
LS1043A and LS2080A.
- Add support for LS1046A SoC, which has similar peripherals as
LS1043A but integrates 4 A72 cores.
- Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB.
* tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: ls2080a: Add TMU device tree support for LS2080A
arm64: dts: ls1043a: Add TMU device tree support for LS1043A
arm64: dts: add LS1046A-QDS board support
Documentation: DT: Add entry for QorIQ LS1046A-QDS board
arm64: dts: add LS1046A-RDB board support
Documentation: DT: Add entry for QorIQ LS1046A-RDB board
arm64: dts: add QorIQ LS1046A SoC support
dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a
dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen
dt-bindings: i2c: adds two more nxp devices
dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG
dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings
Signed-off-by: Olof Johansson <olof@lixom.net>
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Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Both the LS1043A and LS2080A platforms are affected by the Freescale
A008585 erratum. Advertise it in their respective device trees.
Signed-off-by: Scott Wood <oss@buserror.net>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
Pull libata updates from Tejun Heo:
- Write same support added
- Minor ahci MSIX irq handling updates
- Non-critical SCSI command translation fixes
- Controller specific changes
* 'for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
ahci: qoriq: Revert "ahci: qoriq: Disable NCQ on ls2080a SoC"
libata: remove <asm-generic/libata-portmap.h>
libata: remove unused definitions from <asm/libata-portmap.h>
pata_at91: Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
ata: Replace BUG() with BUG_ON().
ata: sata_mv: Replacing dma_pool_alloc and memset with a single call dma_pool_zalloc.
libata: Some drives failing on SCT Write Same
ahci: use pci_alloc_irq_vectors
libata: SCT Write Same handle ATA_DFLAG_PIO
libata: SCT Write Same / DSM Trim
libata: Add support for SCT Write Same
libata: Safely overwrite attached page in WRITE SAME xlat
ahci: also use a per-port lock for the multi-MSIX case
ARM: dts: STiH407-family: Add ports-implemented property in sata nodes
ahci: st: Add ports-implemented property in support
ahci: qoriq: enable snoopable sata read and write
ahci: qoriq: adjust sata parameter
libata-scsi: fix MODE SELECT translation for Control mode page
libata-scsi: use u8 array to store mode page copy
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* dt/irq-fix:
arm64: dts: Fix broken architected timer interrupt trigger
This resolves a non-obvious conflict between a bugfix from
v4.8 and a cleanup for the exynos7 platform.
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The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).
A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.
The respective maintainers are of course welcome to prove me wrong.
While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).
Acked-by: Duc Dang <dhdang@apm.com>
Acked-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.
The PCI IP block of ls2080a has this capability, so adding this
feature to improve the PCI performance.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add DDR memory controller nodes to enable EDAC driver.
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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By default the SATA IP on the qoriq SoCs does not generating
coherent/snoopable transactions. This patch enable it in the
sata axicc register.
In addition, the dma-coherent property must be set on the
SATA controller nodes.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
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Adds the cache nodes and next-level-cache property for the
cacheinfo to work.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and
LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1,
since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update
the #address-cells and reg properties accordingly.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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updates to the fsl-mc node for full functionality:
-msi-parent is needed for interrupt support
-ranges is needed to enable the bus driver to translate bus addresses
-dpmac nodes provide a basis for relating dpmac objects to PHYs
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The compatible "fsl,qoriq-gpio" is used by gpio driver:
drivers/gpio/gpio-mpc8xxx.c to implement general gpio
functionalities.
The chip-specific compatible "fsl,ls2080a-gpio" may be
used to fix potential gpio IP block errata or other
chip-specific gpio issues.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Acked-by: Han xu <han.xu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann:
"The arm64 device tree changes make up an increasing portion of the
overall changes, so they are kept separate from the 32-bit devicetree
changes and from the other arm64 updates.
Newly added SoCs and boards are:
- 96Boards Husky board
- AMD Overdrive board
- Amlogic S905 SoC and related Tronsmart boxes
- Annapurna Labs Alpine family and development board
- Broadcom Vulcan servers
- Broadcom Northstar 2 SoC
- Marvell Armada 3700 family and development board
- Qualcomm MSM8996 SoC
Additional devices are enabled for existing platforms from Applied
Micro, Hisilicon, Mediatek, Qualcomm, and Renesas and there are a
couple of other updates for Rockchip, Xilinx and NXP/Freescale"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (102 commits)
ARM64: dts: amlogic: Add Tronsmart Vega S95 configs
Documentation: devicetree: amlogic: Document Tronsmart Vega S95 boards
ARM64: dts: Prepare configs for Amlogic Meson GXBaby
Documentation: devicetree: amlogic: Document Meson GXBaby
devicetree: bindings: Add vendor prefix for Tronsmart
arm64: dts: qcom: Fix MPP's function used for LED control
arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi
arm64: dts: add the Alpine v2 EVP
arm64: dts: marvell: re-order Device Tree nodes for Armada AP806
arm64: dts: marvell: update Armada AP806 clock description
arm64: dts: marvell: add Device Tree files for Armada 7K/8K
arm64: dts: apm: Add DT node for X-Gene v2 SLIMpro Mailbox I2C Driver
arm64: dts: apm: Mailbox device tree node for APM X-Gene v2 platform.
arm64: dts: apm: Add DT node for X-Gene v1 SLIMpro Mailbox I2C Driver
arm64: dts: apm: mailbox device tree node for APM X-Gene platform.
arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms
arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms
arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms
arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2
arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2
...
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The patch adds LS2085a to PCIe compatible to fix the compatibility
issue when using firmware with LS2085a compatible property.
Signed-off-by: Minghuan Lian <minghuan.lian@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add "snps,quirk-frame-length-adjustment" property to
USB3 node for erratum A009116. This property provides
value of GFLADJ_30MHZ for post silicon frame length
adjustment.
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Olof Johansson:
"This is the first release where we split up the 64-bit contributions a
bit more, and in particular we are having a separate DT branch for
them.
Contents:
- New devices added to Broadcom NorthStar2
- Misc fixes for Exynos7 boards
- QCOM updates for MSM8916
- Rockchip tweaks for rk3368 SoC and eval board
- A series of fixes for APM X-Gene v1 and v2
- Renesas R8A7795 CPU/PSCI additions
- Marvell Berlin4CT PSCI, cpuidle, watchdog portions
- Freescale LS1043a SoC and dev board support
+ some treewide or other misc changes"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (104 commits)
dts/ls2080a: Update DTSI to add support of SP805 WDT
Documentation: DT: Add entry for ARM SP805-WDT
arm64: dts: X-Gene v2: I2C1 clock is always on
arm64: dts: X-Gene v1: I2C0 clock is always on
arm64: dts: Fix to use standard DT node names for X-Gene 1 and X-Gene 2 platforms
arm64: dts: hikey: add label properties to UARTs
arm64: dts: apq8016-sbc: add label properties for UART, I2C, and SPI
arm64: dts: apq8016-sbc: enable UART0 on LS connector
arm64: dts: juno: Add idle-states to device tree
arm64: dts: Added syscon-reboot node for FSL's LS2080A SoC
arm64: dts: add LS1043a-RDB board support
arm64: dts: add Freescale LS1043a SoC support
Documentation: DT: Add entry for Freescale LS1043a-RDB board
arm64: dts: uniphier: add PH1-LD10 SoC/board support
arm64: renesas: r8a7795: fix SATA clock assignment
arm64: dts: salvator-x: Enable SATA controller
arm64: dts: r8a7795: Add SATA controller node
arm64: renesas: r8a7795: add internal delay for i2c IPs
arm64: renesas: salvator-x: Add board part number to DT bindings
arm64: dts: r8a7795: Add pmu device nodes
...
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This patch updates the LS2080a DTSI (DTS Include) file to add
support for eight SP805 Watchdog units which can be used to
reset the eight Cortex-A57 cores available on LS2080A.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Added sys-reboot node to the FSL's LS2080A SoC DT to leverage
the ARM-generic reboot mechanism for this SoC. This mechanism
is enabled through CONFIG_POWER_RESET_SYSCON.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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The GPIO block for ls2080a platform has little endian registers,
the GPIO driver needs this property to read/write registers by
right interface.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
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Add the "little-endian" property to fix the issue that eSDHC
is not working and dumping out "mmc0: Controller never released
inhibit bit(s)." error messages constantly.
Fixes: 5461597f6ce0 ("dts/ls2080a: Update DTSI to add support of various peripherals")
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
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Checkpatch complains about the text suggesting writing to
Free Software Foundation for GPLv2 license copy.
This patch removes the same from the .dtsi and .dts
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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This patch updates the LS2080a DTSI (DTS Include) file to add
support for the following peripherals:
- USB 3.0 Host
- PMU
- CCN-504
- SATA
- SPI
- PCIe
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Freescale is renaming the LS2085A SoC to LS2080A. This patch
addresses the same.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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