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The dpu node 'interrupts' and 'interrupt-names' properties should
reflect all dpu interrupts including the missing 'reserved' interrupt.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
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This patch corrects display LPCG clocks in DC1 subsystem by
s/dc0_disp_lpcg/dc1_disp_lpcg/.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds dc1_pc phandle for dpu2 node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds pixel combiner device tree node support
for the i.MX8 DC1 subsystem.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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phandles for dpu2
This patch adds dc1_dpr1_channel3 and dc1_dpr2_channel1-3 phandles for dpu2
node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds dc1_dpr1_channel3 and dc1_dpr2_channel1-3 device tree
nodes support for i.MX8 DC1 subsystem.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds dc1_prg3 to dc1_prg9 device tree nodes support
for i.MX8 DC1 subsystem.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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add dpr channel 1 and 2 to support DPU blit engine
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
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disp0/1 lpcg clocks parent are fixed.
so dc0/1_disp0/1 clocks couldn't replace by disp0/1_lpcg clocks.
Add dc0/1 disp clocks and disp0/1_lpcg clocks for dc0/1.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
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This patch adds dc0/1_prg1/2 and dc0/1_dpr1_channel1/2 support for
DC0/1 subsystems.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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dpu0/1
This patch uses dc0/1_disp_lpcg clocks as disp0/1 clocks of dpu0/1.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds dc0/1_displ_lpcg clocks to DC0/1 subsystem device trees.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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Currently, all DPUs in i.MX8qm/qxp have the same clocks - pll0/1,
bypass0 and disp0/1. So add the common clocks in imx8-ss-dc0/1.dtsi.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds DC1 subsystem support.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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