Age | Commit message (Collapse) | Author |
|
60MHz is the maximum frequency mentioned in the datasheet for
master mode. Set that to 60MHz to match lpspi2.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
|
|
This commit adds io-channel-cells property to the ADC node. This
property is required in order for an IIO consumer driver to work.
Especially required for Apalis iMX8 QM, as the touchscreen driver
uses ADC channels with the ADC driver based on IIO framework.
Based on commit 9b1793afe.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit bf8bd47a50e853f5cf6c34dbe6186853527714fc)
Conflicts:
arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
The file moved to arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
put the respective lines in there
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
|
|
Combined interrupt number may cause unexcepted irq event when using DMA
and too many interrupts are generated.
So change all spi and i2c interrupts number to non-combined for
imx8qxp/8qm/8dxl.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
|
|
Currently, the adma_lcdif and it's related nodes are duplicated in 8qxp
and 8dxl dts files. Since it's the same subsystem, move these nodes into
generic files, so that both 8qxp and 8dxl dts files can use them.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
|
|
Add DMA configurations for LPSPI nodes on i.MX8QX/QM/DXL.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
|
|
Add lpspi mater and slave dts files for imx8qxp/qm platforms.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
|
|
Split dma channel power domain from sub-domain of dma customer driver
such as Audio, LPUART etc.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
|
|
Add emvsim device node for imx8qm mek.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
(cherry picked from commit e4586a8fddc499296abc1442ff3291559fb77e97)
|
|
Add ipg clock config for all lpi2c bus.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
|
|
Add partition reset function for i.MX8QM/QXP.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
|
|
Add ADC support for imx8qm-mek board.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
|
|
Enable LPSPI2 function on imx8qm-mek board. LPSPI2 pinout are on the
base board.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
|
|
convert enet&uart clock to new binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
|
|
From HW point of view, CAN1/2 do not depend on CAN0 PD, it just uses
CAN0 clock which could be handled by clock driver itself. Now clock
runtime pm has support it, so drop multi-pd for CAN1/2.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
|
|
fully switched to new clk binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
|
|
amda ss is consisted of dma and audio ss in qxp which are
also used in qm.
Let's split them into two ss for better code reuse.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
|