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Add the iMX8QXP PCIe EP mode, and verified on MEK board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
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- Enable the PCIEB port on the i.MX8QM MEK and base board.
- In the PCIEAX1PCIEBx1SATA usecase, the PHYX2_PCLK[0] is mandatory
required by PCIEB. Otherwise PCIEB can't link up when exist from
L2 mode when only PCIEB is used.
- PCIEB has one more PER clock, since that the PCIEA CSR register
would be configuired when PCIEB is initialized.
- Regarding to the base board HW limitation(two Disable#) are not
connected. Only the standard PCIe EP device is supported on PCIEB port.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
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Enable the imx pcie ep verification solution.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
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External 100Mhz differential OSC is used as HSIO REF clock source, so
set it as the parent clk of the PHY PCLK.
Then add the fixed HSIO REF clocks regarding the different HSIO use
cases.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
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Enable imx8qm pciea and sata
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
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move pciea into qm hsio ss
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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fully switched to new clk binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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Add the hsio pcie support for imx8qm/qxp.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
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