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The power domains are causing the i2c expander to be reset during suspend resume. After resume the expander state is not being restored properly. So since the reset is optional, I am removing the power domains.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Reviewed-by: Shenwei Wang <shenwei.wang@nxp.com>
(cherry picked from commit b928f18fdf653d70871958f561357ad98fa4aa86)
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I2c chip are reset when the partition reboots.
A partition reboot has to reset the ones used by a specific OS.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
(cherry picked from commit 3362e480195360303b60b17d0c563f0c837c6f58)
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
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EXP2_INT_B is low when evk power on and it is hight when press reset
botton.
U84 PCA6416 have not reset correct when board power on.
Reset it by toggle I2C_EXP4_P0.2
[ 55.885169] irq 162: nobody cared (try booting with the "irqpoll" option)
[ 55.891980] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.4.70-2.3.0+g4f2631b022d8 #1
[ 55.899641] Hardware name: Freescale i.MX8DXL EVK (DT)
[ 55.904784] Call trace:
[ 55.907244] dump_backtrace+0x0/0x140
[ 55.910911] show_stack+0x14/0x20
[ 55.914233] dump_stack+0xb4/0x114
[ 55.917638] __report_bad_irq+0x48/0xd4
[ 55.921475] note_interrupt+0x2c4/0x388
[ 55.925318] handle_irq_event_percpu+0x80/0x88
[ 55.929762] handle_irq_event+0x44/0xd8
[ 55.933603] handle_level_irq+0xb4/0x138
[ 55.937531] generic_handle_irq+0x24/0x38
[ 55.941547] mxc_gpio_irq_handler+0x48/0x138
[ 55.945817] mx3_gpio_irq_handler+0x80/0xe8
[ 55.950004] generic_handle_irq+0x24/0x38
[ 55.954020] __handle_domain_irq+0x60/0xb8
[ 55.958120] gic_handle_irq+0x5c/0x148
[ 55.961872] el1_irq+0xb8/0x180
[ 55.965019] arch_cpu_idle+0x10/0x18
[ 55.968598] do_idle+0x200/0x280
[ 55.971826] cpu_startup_entry+0x24/0x80
[ 55.975756] rest_init+0xd4/0xe0
[ 55.978989] arch_call_rest_init+0xc/0x14
[ 55.982998] start_kernel+0x418/0x44c
Signed-off-by: Frank Li <Frank.Li@nxp.com>
(cherry picked from commit 7dd0691d6293ed3f020319ecb1dbb5c6262b9821)
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
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According to board team signal measure result and update trim value as
For USB OTG1, setting 0x5b100010=0X10080802 (default 0X10080807).
For USB OTG2, setting 0x5b110010=0X10080803 (default 0X10080807).
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Peter Chen <peter.chen@nxp.com>
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With MCU SDK 2.9, there are two copy resource tables published to Linux,
the 1st is vdev0vring0, the 2nd is in rsc-table address.
The 1st is for legacy compatible usage, it will be removed in future
releases. we will only use 2nd new address in future releases.
But at current stage, we still use the 1st one in linux, but we
also need to reserve area for the 2nd one, otherwise when using
linux to kick Mcore, Mcore might overwrite the data used by Linux.
The 2nd table address is as below:
8QXP/DX/DXL: [0x90000000 + 1M – 4KB, 0x90000000 + 1M)
8QM: CM40: [0x90000000 + 1M – 4KB, 0x90000000 + 1M)
CM41: [0x90100000 + 1M – 4KB, 0x90100000 + 1M)
8MQ/MM/MN-evk: [0xb8000000 + 1M – 4KB, 0xb8000000 + 1M)
8MP-evk: [0x55000000 + 1M – 4KB, 0x55000000 + 1M)
Currently only 8DXL and 8MP use MCU SDK 2.9 and others still use MCU
SDK 2.8, but for prepare future update, we update all SoC to reserve
the 2nd table address.
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Added dedicate compatible string for DXL to use IPS to read data for
DXL.
Signed-off-by: Han Xu <han.xu@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
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of pcie nodes
Remove the reserved-region property of pcie nodes for imx8m and imx8
platform since for the new pcie frame, we don't need them any more.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
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Disable the pull control for pad, otherwise the pull up or
pull down will cause the signal abnormal on TX line, then
there is noise.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Peng Zhang <peng.zhang_8@nxp.com>
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The "enable-active-high" property should be added when always on is
required by the fixed regulator.
Otherwise, the clk_ext_sel would be changed to low after the
initialization of the regulator is complete. And PCIe wouldn't
works well.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
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A1 chip already fix pcie issue, so enable pcie in imx8dxl-evk.dts,
and remove the extra file "*-pcie.dts".
Current BSP doesn't support A0 chip after the change.
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Add the iMX8DXL PCIe EP support and verified on EVK board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
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Different "arecords" tasks getting i2c_adapter_lock_bus and
clk_prepare_lock at the same time cause the deadlock.
Task A gets the clk_prepare_lock and waiting for the
i2c_adapter_lock_bus when it tries to open MCLK which is gated by
a pin of IO Expander on the same i2c bus.
Task B gets the i2c_adapter_lock_bus and waiting for the
clk_prepare_lock when configs wm8960 through i2c.
The usages of i2c mux, i2c device and clock prepare lock do not have
obvious error.
So, avoid the deadlock by using "pinctrl-assert-gpios"
to set the GPIO gate of MCLK when kernel boot instead of using
"gpio-gate-clock" to set the GPIO gate every time using it.
Task A blocked call trace:
[ 112.367398] Call trace:
[ 112.369840] __switch_to+0x104/0x170
[ 112.373420] __schedule+0x224/0x560
[ 112.376910] schedule+0x40/0xe0
[ 112.380050] __rt_mutex_slowlock+0x60/0xf8
[ 112.384150] rt_mutex_slowlock+0xac/0x188
[ 112.388164] rt_mutex_lock+0x58/0x60
[ 112.391750] i2c_adapter_lock_bus+0x10/0x18
[ 112.395939] i2c_transfer+0x4c/0xf8
[ 112.399430] i2c_transfer_buffer_flags+0x58/0x80
[ 112.404058] regmap_i2c_write+0x1c/0x50
[ 112.407893] _regmap_raw_write_impl+0x514/0x610
[ 112.412427] _regmap_bus_raw_write+0x60/0x78
[ 112.416701] _regmap_write+0x58/0xa8
[ 112.420281] _regmap_update_bits+0xf0/0x108
[ 112.424468] regmap_update_bits_base+0x60/0x90
[ 112.428923] pca953x_gpio_set_value+0xac/0xc8
[ 112.433284] gpiod_set_value_nocheck+0x54/0x98
[ 112.437726] gpiod_set_value_cansleep+0x38/0x48
[ 112.442264] clk_sleeping_gpio_gate_prepare+0x14/0x20
[ 112.447321] clk_core_prepare+0x58/0xe0
[ 112.451155] clk_prepare+0x24/0x40
[ 112.454571] wm8960_set_bias_level_out3+0x120/0x1f8
Task B blocked call trace:
[ 115.927987] Call trace:
[ 115.930429] __switch_to+0x104/0x170
[ 115.934001] __schedule+0x224/0x560
[ 115.937491] schedule+0x40/0xe0
[ 115.940638] schedule_preempt_disabled+0x20/0x38
[ 115.945260] __mutex_lock.isra.0+0x17c/0x5b8
[ 115.949532] __mutex_lock_slowpath+0x10/0x18
[ 115.953808] mutex_lock+0x34/0x50
[ 115.957131] clk_prepare_lock+0x40/0x98
[ 115.960968] clk_core_get_rate+0x14/0x70
[ 115.964895] clk_get_rate+0x14/0x28
[ 115.968393] lpi2c_imx_xfer+0x78/0x610
[ 115.972144] __i2c_transfer+0x14c/0x390
[ 115.975979] i2c_smbus_xfer_emulated+0xd8/0x630
[ 115.980513] __i2c_smbus_xfer+0x118/0x210
[ 115.984529] pca954x_select_chan+0x74/0xb8
[ 115.988628] __i2c_mux_master_xfer+0x38/0x80
[ 115.992903] __i2c_transfer+0x14c/0x390
[ 115.996743] i2c_transfer+0x5c/0xf8
[ 116.000236] i2c_transfer_buffer_flags+0x58/0x80
[ 116.004859] regmap_i2c_write+0x1c/0x50
[ 116.008696] _regmap_bus_formatted_write+0x6c/0xb8
[ 116.013489] _regmap_write+0x58/0xa8
[ 116.017071] regmap_write+0x48/0x70
[ 116.020564] snd_soc_component_write+0x30/0x40
[ 116.025015] wm8960_set_pll+0x1e8/0x210
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
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Add property fsl,spi-only-use-cs1-sel to mark this board only uses
CS1 without CS0.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
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files
Enable cm40 lpuart in imx8dxl-evk.dts and disable it in
imx8dxl-evk-rpmsg.dts.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Enable lpspi3 by default for imx8dxl-evk and imx8dxl-ddr3-evk.
Add imx8dxl-evk-lpspi-slave.dtb to support lpspi3 slave mode on
imx8dxl-evk.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
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Add extra pcie dts file to enable wireless (like NXP
88w8997 and CYPRESS 4356/4359) since most of A0 chips
pcie has issue, which is convenient for tester to verify
wireless on comming release with golden chips.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Add cm4 node for remoteproc usage.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Enable the PCIe EP/RC verification on iMX8DXL EVK board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
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Add mac address support by reading from efuse.
Reviewed-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Correct the legacy INTX numbers of the iMX8DXL PCIe.
Use the internal PLL as PCIe REF clock.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
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The power domain for clocks is not needed by audio drivers, which
is handled by clock driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
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Enable SAI/ASRC/WM8960
1. Update the interrupt number for audio modules
2. Enable 3 wm8960 codecs
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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correct property name. power-active-high
USB OTG2 power pin function set problem is fixed by scfw
848498bf4c6d79b33cc5018969574a5369479bc4
Signed-off-by: Frank Li <Frank.Li@nxp.com>
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Enable legacy enet0 port to support daughter RGMII AR8031
PHY board.
imx8dxl evk board rework:
- Remove U30, R181, R182
- Connect U30.2 -U30.7
- Connect U30.3 ->U30.6
- Change R178/R179 to 1.5K
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Enable HIF PCIe for wlan, uart for bluetooth.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Correct board name
Signed-off-by: Frank Li <Frank.Li@nxp.com>
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iMX8DXL EVK board only has 1GB DDR, so it can't allocate 960MB CMA.
Change the CMA size to 320M to align with 8DX.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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Enable ADC0, tested by internal 1.2v.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
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BL32 base address is set within the first 1GByte of DDR.
As a new rule it will be set at base address + 0x16000000.
This new position will relax current dependency of the OPTEE
base address on the size of the DDR.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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limited max frequency to 100M
Signed-off-by: Frank Li <Frank.Li@nxp.com>
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DXL use usb pwr alternate function in pinmux.
Needn't GPIO regulator
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
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basic host and peripheral work
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
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Enable FlexCAN on i.MX8DXL EVK board.
Acked-by: Fugang Duan <Fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
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Add lpspi3 for imx8dxl-evk. According to the schematic, disable it
by default to support display functions.
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
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Add i2c3 node.
Correct the place of pca9548 to i2c2 and i2c3.
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
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usb peripherial and host basic function work
Signed-off-by: Frank Li <Frank.Li@nxp.com>
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Add eqos support for imx8dxl evk board.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Add DT support for i.MX8DXL.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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