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2021-01-11arm64: dts: imx8m: change ocotp node name on i.MX8M SoCsAnson Huang
Change OCOTP node name from ocotp-ctrl to efuse to be compliant with yaml schema, it requires the nodename to be one of "eeprom|efuse|nvram". Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> (cherry picked from commit 12fa1078efc871604d62e992cb8a038421b82096) Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2021-01-11arm64: dts: imx8mm: Remove incorrect fallback compatible for ocotpAnson Huang
Compared to i.MX7D, i.MX8MM has different ocotp layout, so it should NOT use "fsl,imx7d-ocotp" as ocotp's fallback compatible, remove it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> (cherry picked from commit b09802a03f0390fc115bf4ce4683645dc9b090bd) Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2020-11-19MLK-24998-8 arm64: dts: imx8mm: assign osc_24m to dsi PHY REF clock sourceFancy Fang
Due to commit b3a420c9cf3f (MLK-24998-4 drm/bridge: sec-dsim: use 12MHz for default PHY REF clock), the dsi PHY reference clock source need to be assigned to osc_24m clock. Signed-off-by: Fancy Fang <chen.fang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 2972241b831ed65f641ccdb80b504cadef0ba591)
2020-08-13arm64: dts: imx8mq/mm/mn: add caam snvs clockHoria Geantă
On i.MX8M* the snvs clock is mandatory cf. DT binding doc, add it. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Franck Lenormand <franck.lenormand@nxp.com>
2020-08-11MLK-24483-3: arm64: dts: imx8mm: changed to imx51-ecspi typeRobin Gong
Changed ecspi compatible name to imx51-ecspi instead of imx6ul-ecspi since ERR009165 not fix on i.mx8mm. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
2020-06-11MLK-24012-06 arm64: dts: add imx8m pcie ep supportRichard Zhu
Add the PCIe EP mode on iMX8MQ/MM/MP platforms. And enable the EP mode on EVK boards. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-05-12MLK-23923: dts: arm64: freescale: imx8mm sai mclk0 dummy clkAdrian Alonso
Add missing sai mclk0 dummy clk expected by SAI driver, fix error: fsl-sai 30020000.sai: failed to get mclk0 clock: -2 Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
2020-04-27MLK-23844-2 ARM64: dts: freescale: imx8mm: correct VDDARM@1.6GHzRobin Gong
Correct VDDARM to 0.95V@1.6Ghz with datasheet. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-04-17MLK-23792-2: arm64: dts: imx8mm: Enable sai6 for monitorring spdic rx clockShengjiu Wang
Enable sai6 for monitorring spdic rx clock Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2020-03-05arm64: dts: imx8mm: align CAAM Job ring node namingSilvano di Ninno
Align i.MX 8mm Job ring node naming with the rest of the i.MX 8 platforms. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
2019-12-19MLK-23131-1 arm64: dts: imx8mm/imx8mn: Add dram_pll_div clock for busfreqAnson Huang
On i.MX8MM/i.MX8MN platforms, need to add dram_pll_div clock for busfreq driver to update dram_core clock when DRAM frequency switches between low bus mode and high bus mode. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Robin Gong <yibin.gong@nxp.com>
2019-11-27MLKU-25-4 arm64: dts: imx8m: add secure memoryHoria Geantă
Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-11-27MLKU-38-5 arm64: dts: imx8m: add caam snvs and secvioHoria Geantă
Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-11-27arm64: dts: enable the imx pcie ep verification solutionRichard Zhu
Enable the imx pcie ep verification solution. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2019-11-26LF-68-3: ARM64: dts: freescale: imx8mm/mq: add clock property for snvs-pwrkeyRobin Gong
Add clock property for snvs-pwrkey. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2019-11-25arm64: dts: imx8mm: add fsl,dataline for SAI nodeShengjiu Wang
Add fsl,dataline for SAI node Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25arm64: dts: imx8mm: rename apb clock names for dispmix resetFancy Fang
Rename the apb clock names from 'apb-clk' to 'disp_apb_root_clk' for dispmix reset nodes, since in commit f541de184245(reset: imx8m: Correct clock name for dispmix driver), it changes the apb clock name. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2019-11-25arm64: dts: imx8mm: Define resets for LCDIF and DSIMFancy Fang
The dispmix-reset device can be used to control the LCDIF and DSIM bus reset and clock enable. So define 'resets' property for both LCDIF and DSIM for this purpose which will be used to replace 'dispmix_gpr' usage. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2019-11-25arm64: dts: imx8mm: Add 'dispmix-reset' deviceFancy Fang
Create a new device node 'dispmix-reset' to describe the reset controller in DISPMIX to control several submodules bus and clock reset and enable. All the reset lines can be divided into three groups: sft_rstn, clk_en and mipi_rst. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2019-11-25ARM64: imx8mm-evk: Move assign clocks of audio PLLs to correct placeShengjiu Wang
Put assigned clocks of audio PLLs in imx8mm-evk.dts, which conflict with the assigned clocks in imx8mm. Fixes: 77b5daa55e63 ("ARM64: dts: imx8mm: Enable AK4497/AK4458/AK5558/SPDIF/MICFIL") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25ARM64: dts: imx8mm: increase cma size to '0x28000000'Zhou Peng
Default is only about 300MB, not enough for some multi-instance test Signed-off-by: Zhou Peng <eagle.zhou@nxp.com> (cherry picked from commit 43b40a50f66d7e6e83775a9568546a92876956d1)
2019-11-25MLKU-123-2 arm64: dts: imx8mm: Add CAAM nodeHoria Geantă
Add node for CAAM - Cryptographic Acceleration and Assurance Module. Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2019-11-25ARM64: dts: imx8mm: add csi bridge and mipi csi nodeRobby Cai
add csi bridge and mipi csi node Signed-off-by: Robby Cai <robby.cai@nxp.com>
2019-11-25arm64: dts: imx8mq/mm/mn: add the enet wakeup supportFugang Duan
Add the wakeup irq property as the system wakeup source. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2019-11-25arm64: dts: imx8mm: Add GPU device for 8MMElla Feng
Add gpu in device tree: arch/arm64/boot/dts/freescale/imx8mm.dtsi arch/arm64/boot/dts/freescale/imx8mm-evk.dts Signed-off-by: Ella Feng <ella.feng@nxp.com> [ Aisheng: remove unecessary new blank line ] Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2019-11-25ARM64: dts: imx8mm: Enable AK4497/AK4458/AK5558/SPDIF/MICFILShengjiu Wang
Enable AK4497/AK4458/AK5558/SPDIF/MICFIL Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25arm64: dts: imx845: add vpu encoderZhou Peng
enable 845 h1 in device tree Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
2019-11-25arm64: dts: imx845: add vpu decoderZhou Peng
enable 845 g1/g2 in device tree Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
2019-11-25ARM64: dts: imx8mm: re-order display nodesFancy Fang
The devices in the device tree are registered in the top-down order. But when system suspend entered, the device tree is walked in a bottom-up order to suspend devices. So change the display device nodes register order to be: LCDIF -> SEC DSIM -> Display Subsystem Since in display subystem, it will disable the whole display pipeline. So this should be first suspended before LCDIF and SEC DSIM. And besides, the SEC DSIM is better to be suspended before LCDIF which is the same with the sequence for display pipeline disables. And when system resume entered, the devices resume sequence is: LCDIF -> SEC DSIM -> Display Subsystem Which is a top-down order and is the correct sequence for display devices resume. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2019-11-25ARM64: dts: imx8mm: add the clkreq reset for imx8mm pcieRichard Zhu
Add the CLKREQ reset used by L1.1ss feature on iMX8MM PCIe. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-11-25ARM64: dts: imx8mm: correct the imx8mm pcie phy dts nodeRichard Zhu
Correct the reg scope of the iMX8MM PCIe PHY DTS node. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-11-25ARM64: dts: enable pcie on imx8mmRichard Zhu
Enable PCIe on iMX8MM platforms. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-11-25ARM64: dts: imx8mm: add power domain for displayFancy Fang
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2019-11-25ARM64: dts: imx8mm: correct 'reg' property for display nodesFancy Fang
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2019-11-25MLK-22404-03 arm64: dts: freescale: Add power domain nodes for i.mx8mmJacky Bai
Add the power domain nodes for i.MX8MM. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2019-11-25ARM64: dts: imx8mm: add display devices nodesFancy Fang
Add device nodes for display devices, LCDIF, MIPI DSI, Dispmix GPR controller and display subsystem. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2019-11-25arm64: dts: imx8mm: Add thermal zone supportAnson Huang
Add thermal zone and tmu node to support i.MX8MM thermal driver, ONLY cpu thermal zone is supported, and cpu cooling is also added. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-11-25MLK-22041: arm64: dts: one more range entry for fspiHan Xu
add one more range entry for fspi memory area. Signed-off-by: Han Xu <han.xu@nxp.com>
2019-11-25arm64: dts: imx8mm: add nvmem mac address supportFugang Duan
Add nvmem mac address support, then enet controller can read valid mac address from efuse. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2019-11-25MLK-21960-3: arm64: dts: enable fspi in imx8mm dtsHan Xu
enable fspi in imx8mm DT file Signed-off-by: Han Xu <han.xu@nxp.com>
2019-11-25arm64: dts: imx8mm: Add busfreqLeonard Crestez
2019-11-25arm64: dts: imx8m: add the rpmsg supportRichard Zhu
Add the imx8mq/imx8mm rpmsg support. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-11-25ARM64: dts: freescale: imx8mm/8mq: update new compatible name for ecspi and sdmaRobin Gong
Add new 'imx6ul-ecspi' compatible name for ecspi and new 'imx8mq-sdma' name for sdma since on i.mx8mm/mq chip fix ecspi errata. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
2019-10-28arm64: dts: imx8mm: fix compatible string for sdmaShengjiu Wang
SDMA in i.MX8MM should use same configuration as i.MX8MQ So need to change compatible string to be "fsl,imx8mq-sdma". Fixes: a05ea40eb384 ("arm64: dts: imx: Add i.mx8mm dtsi support") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-14arm64: dts: imx8mm: Use correct clock for usdhc's ipg clkAnson Huang
On i.MX8MM, usdhc's ipg clock is from IMX8MM_CLK_IPG_ROOT, assign it explicitly instead of using IMX8MM_CLK_DUMMY. Fixes: a05ea40eb384 ("arm64: dts: imx: Add i.mx8mm dtsi support") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-09-17Merge branch 'timers-core-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull core timer updates from Thomas Gleixner: "Timers and timekeeping updates: - A large overhaul of the posix CPU timer code which is a preparation for moving the CPU timer expiry out into task work so it can be properly accounted on the task/process. An update to the bogus permission checks will come later during the merge window as feedback was not complete before heading of for travel. - Switch the timerqueue code to use cached rbtrees and get rid of the homebrewn caching of the leftmost node. - Consolidate hrtimer_init() + hrtimer_init_sleeper() calls into a single function - Implement the separation of hrtimers to be forced to expire in hard interrupt context even when PREEMPT_RT is enabled and mark the affected timers accordingly. - Implement a mechanism for hrtimers and the timer wheel to protect RT against priority inversion and live lock issues when a (hr)timer which should be canceled is currently executing the callback. Instead of infinitely spinning, the task which tries to cancel the timer blocks on a per cpu base expiry lock which is held and released by the (hr)timer expiry code. - Enable the Hyper-V TSC page based sched_clock for Hyper-V guests resulting in faster access to timekeeping functions. - Updates to various clocksource/clockevent drivers and their device tree bindings. - The usual small improvements all over the place" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (101 commits) posix-cpu-timers: Fix permission check regression posix-cpu-timers: Always clear head pointer on dequeue hrtimer: Add a missing bracket and hide `migration_base' on !SMP posix-cpu-timers: Make expiry_active check actually work correctly posix-timers: Unbreak CONFIG_POSIX_TIMERS=n build tick: Mark sched_timer to expire in hard interrupt context hrtimer: Add kernel doc annotation for HRTIMER_MODE_HARD x86/hyperv: Hide pv_ops access for CONFIG_PARAVIRT=n posix-cpu-timers: Utilize timerqueue for storage posix-cpu-timers: Move state tracking to struct posix_cputimers posix-cpu-timers: Deduplicate rlimit handling posix-cpu-timers: Remove pointless comparisons posix-cpu-timers: Get rid of 64bit divisions posix-cpu-timers: Consolidate timer expiry further posix-cpu-timers: Get rid of zero checks rlimit: Rewrite non-sensical RLIMIT_CPU comment posix-cpu-timers: Respect INFINITY for hard RTTIME limit posix-cpu-timers: Switch thread group sampling to array posix-cpu-timers: Restructure expiry array posix-cpu-timers: Remove cputime_expires ...
2019-08-27arm64: dts: imx8mm: Add system counter nodeAnson Huang
Add i.MX8MM system counter node to enable timer-imx-sysctr broadcast timer driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-08-19arm64: dts: imx8mm: Enable cpu-idle driverAnson Huang
Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states are supported, details as below: root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/name WFI root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/usage 3973 root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/name cpu-pd-wait root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage 6647 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03arm64: dts: imx8mm: Add opp-suspend property to OPP tableAnson Huang
Add opp-suspend property to each OPP, the of opp core will select the OPP HW supported and with highest rate to be suspend opp, it will speed up the suspend/resume process. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03arm64: dts: imx8mm: Correct OPP table according to latest datasheetAnson Huang
According to latest datasheet (Rev.0.2, 04/2019) from below links, 1.8GHz is ONLY available for consumer part, so the market segment bits for 1.8GHz opp should ONLY available for consumer part accordingly. https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf https://www.nxp.com/docs/en/data-sheet/IMX8MMCEC.pdf Fixes: f403a26c865b (arm64: dts: imx8mm: Add cpu speed grading and all OPPs) Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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