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[ Upstream commit b0293c19d42f6d6951c2fab9a47fed50baf2c14d ]
Change sdhcN aliases to mmcN to make them actually work. Currently the
board uses non-standard aliases sdhcN, which do not work, resulting in
mmc0 and mmc1 hosts randomly changing indices between boots.
Fixes: c4da5a561627 ("arm64: dts: qcom: Add msm8916 sdhci configuration nodes")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211201020559.1611890-1-dmitry.baryshkov@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
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[ Upstream commit d5ae2528b0b56cf054b27d48b0cb85330900082f ]
Fix `reserved` and `rfsa` unit address according to their reg address
Fixes: 7258e10e6a0b ("ARM: dts: msm8916: Update reserved-memory")
Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
Link: https://lore.kernel.org/r/20210123104417.518105-1-vincent.knecht@mailoo.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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[ Upstream commit 027cca9eb5b450c3f6bb916ba999144c2ec23cb7 ]
The mdss node sets #interrupt-cells = <1>, so its interrupts
should be referenced using a single cell (in this case: only the
interrupt number).
However, right now the mdp/dsi node both have two interrupt cells
set, e.g. interrupts = <4 0>. The 0 is probably meant to say
IRQ_TYPE_NONE (= 0), but with #interrupt-cells = <1> this is
actually interpreted as a second interrupt line.
Remove the IRQ flags from both interrupts to fix this.
Fixes: 305410ffd1b2 ("arm64: dts: msm8916: Add display support")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-5-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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[ Upstream commit e6859ae8603c5946b8f3ecbd9b4f02b72955b9d0 ]
Commit fe2aff0c574d2 ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points")
removed the unit names for most of the thermal trip points defined
in msm8916.dtsi, but missed to update the one for cpu0_1-thermal.
So why wasn't this spotted by "make dtbs_check"? Apparently, the name
of the thermal zone is already invalid: thermal-zones.yaml specifies
a regex of ^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$, so it is not allowed
to contain underscores. Therefore the thermal zone was never verified
using the DTB schema.
After replacing the underscore in the thermal zone name, the warning
shows up:
apq8016-sbc.dt.yaml: thermal-zones: cpu0-1-thermal:trips: 'trip-point@0'
does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+'
Fix up the thermal zone names and remove the unit name for the trip point.
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Fixes: fe2aff0c574d2 ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-3-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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[ Upstream commit fe2aff0c574d206f34f1864d5a0b093694c27142 ]
The thermal trip points have unit name but no reg property, so we can
remove them. It also fixes the following warnings from 'make dtbs_check'
after adding the thermal yaml bindings.
arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: thermal-zones:
gpu-thermal:trips: 'trip-point@0' does not match any of the regexes:
'^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: thermal-zones:
camera-thermal:trips: 'trip-point@0' does not match any of the regexes:
'^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: thermal-zones:
modem-thermal:trips: 'trip-point@0' does not match any of the regexes:
'^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/msm8916-mtp.dt.yaml: thermal-zones:
gpu-thermal:trips: 'trip-point@0' does not match any of the regexes:
'^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/msm8916-mtp.dt.yaml: thermal-zones:
camera-thermal:trips: 'trip-point@0' does not match any of the regexes:
'^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/msm8916-mtp.dt.yaml: thermal-zones:
modem-thermal:trips: 'trip-point@0' does not match any of the regexes:
'^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+'
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Link: https://lore.kernel.org/r/2d3d045c18a2fb85b28cf304aa11ae6e6538d75e.1585562459.git.amit.kucheria@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm ARM64 Updates for v5.3
* Switch to use second gen PON on PM8998
* Add PSCI cupidle states for MSM8996, MSM8998,and SDM845
* Add MSM8996 UFS phy reset controller
* Add propre cpu capacity scaling on MSM8996
* Fixups for APR domain, legacy clocks, and PSCI entry latency on MSM8996
* Enable SMMUs on MSM8996
* Add Dragonboard 845C
* Add Q6V5, GPU, GMU, and AOSS QMP node on SDM845
* Fixup CPU topology on SDM845
* Change USB1 to be peripheral on SDM845 MTP
* Add PCIe Phy, RC nodes, ANOC1 SMMU, and RPMPD node on MSM8998
* Update coresight bindings for MSM8916
* Update idle state names and entry-method on MSM8916
* Add PCIe, RPMPD, LPASS, Q6, TCSR, TuringCC, PSCI cpuidle states,
and CDSP on QCS404
* Add reset-cells property to QCS404 GCC node
* Fixup s3 max voltage, l3 min voltage, drive strength typo, and
s3 supply definition on QCS404-evb
* Fixup ADC outputs and VADC calibration on PMS405
* tag 'qcom-arm64-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (39 commits)
arm64: dts: qcom: qcs404-evb: fix vdd_apc supply
arm64: dts: qcom: pm8998: Use qcom,pm8998-pon binding for second gen pon
arm64: dts: qcom: msm8996: Enable SMMUs
arm64: dts: qcom: msm8996: Correct apr-domain property
arm64: dts: qcom: Add Dragonboard 845c
arm64: dts: qcom: qcs404-evb: Enable PCIe
arm64: dts: qcom: qcs404: Add PCIe related nodes
arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes
arm64: dts: qcom: msm8998: Add ANOC1 SMMU node
arm64: dts: qcom: msm8996: Stop using legacy clock names
arm64: dts: msm8996: fix PSCI entry-latency-us
arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states
arm64: dts: qcom: sdm845: Add Q6V5 MSS node
arm64: dts: qcom: Add AOSS QMP node
arm64: dts: qcom-qcs404: Add reset-cells to GCC node
arm64: dts: qcom-msm8916: Update coresight DT bindings
arm64: dts: qcom: msm8998: Add rpmpd node
arm64: dts: qcom: qcs404: Add rpmpd node
arm64: dts: qcom: qcs404: Move lpass and q6 into soc
arm64: dts: qcom: qcs404: Fully describe the CDSP
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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CoreSight DT bindings have been updated, thus the old compatible strings
are obsolete and the drivers will report warning if DTS uses these
obsolete strings.
This patch switches to the new bindings for CoreSight dynamic funnel,
so can dismiss warning during initialisation.
Cc: Andy Gross <agross@kernel.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
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Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 and
only version 2 as published by the free software foundation this
program is distributed in the hope that it will be useful but
without any warranty without even the implied warranty of
merchantability or fitness for a particular purpose see the gnu
general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 294 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Instead of using Qualcomm-specific terminology, use generic node names
for the idle states that are easier to understand. Move the description
into the "idle-state-name" property.
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
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The idle-states binding documentation[1] mentions that the
'entry-method' property is required on 64-bit platforms and must be set
to "psci".
[1] Documentation/devicetree/bindings/arm/idle-states.txt (see
idle-states node)
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
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Add 'xo_board' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 28nm PHY.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Andy Gross <agross@kernel.org>
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We don't have any cooling-devices related to the camera. Use the "hot"
trip type so allow the temperature to be exported to userspace and
remove the "critical" trip.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
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Maintain naming consistency with what was landed for sdm845. Simplifies
parsing for test tools.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
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On platforms that have a modem, sensor 0 monitors the modem.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt
Qualcomm ARM64 Updates for v5.1
* Add thermal trip points to cpufreq
* Add SDM845 IOMMU info for SDHC, USB, and WLAN
* Fix MSM8916 clock cell argument
* tag 'qcom-arm64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: sdm845: Fixup dependency on RPMPD includes
arm64: dts: sdm845: Add clocks and iommus to WCN3990 WLAN node
arm64: dts: qcom: sdm845: Define iommus for USB controllers
arm64: dts: qcom: sdm845: Define IOMMU for sdhc 2
arm64: dts: sdm845: wireup the thermal trip points to cpufreq
arm64: dts: msm8916: remove bogus argument to the cpu clock
[arnd: I've pulled the earlier branch again after an update, this
adds the stuff listed above, and fixes a build error from the missing
dependency, as I requested]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The apcs node has #clock-cells = <0>, which means that those who
references it should specify 0 arguments.
The apcs reference in the cpu node incorrectly specifies an argument,
remove this bogus argument.
Fixes: 65afdf458360 ("arm64: dts: qcom: msm8916: Add CPU frequency scaling support")
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.
This fixes warnings generated by the DT schema.
Reported-by: Michal Simek <michal.simek@xilinx.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
Acked-by: Robert Richter <rrichter@cavium.com>
Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add a node for the Camera Subsystem present on the Qualcomm
MSM8916 SoC.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add IOMMU sub-node for VFE secure context bank.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Initialise the camera thermal zone to export temperature to userspace.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Initialise the gpu thermal zone to export temperature to userspace.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This new property allows the number of sensors to be configured from DT
instead of being hardcoded in platform data. Use it.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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We've earlier added support to split the register address space into TM
and SROT regions. Split up the regmap address space into two for msm8916
that has a similar register layout.
Since tsens-common.c/init_common() currently only registers one address
space, the order is important (TM before SROT). This is OK since the
code doesn't really use the SROT functionality yet.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Switch to updated coresight bindings for hw ports
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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DTS board files should always specify model and compatible.
All DTS board files that includes msm8916.dtsi
already specifies model and compatible, and will thus
override the model and compatible in msm8916.dtsi.
Drop model and compatible from msm8916.dtsi,
since they are only a source of confusion.
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt
Qualcomm ARM64 Updates for v4.19
* Add support for PM8005/PM8998 and related nodes
* Add/fix nodes on SDM845 for I2c, SPI, UART, and RPMH
* Fix BT LED trigger on DB410c
* Drop legacy clock names on MSM8916
* Add gpio line names on DB820c
* tag 'qcom-arm64-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: qcom: db410c: Fix Bluetooth LED trigger
arm64: dts: sdm845: Default qupv3_id_0 as "disabled" like _id_1
arm64: dts: msm8916: drop legacy suffix for clocks used by MSM DRM driver
arm64: dts: qcom: db820c: Add gpio-line-names property
arm64: dts: sdm845: Add rpmh-clk node
arm64: dts: sdm845: Add rpmh-rsc node
arm64: dts: qcom: sdm845: Enable debug UART and I2C10 on sdm845-mtp
arm64: dts: qcom: sdm845: Add I2C, SPI, and UART9 nodes
arm64: dts: qcom: Add pm8005 and pm8998 support
arm64: dts: qcom: Add pmu node to sdm845
Signed-off-by: Olof Johansson <olof@lixom.net>
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Drop legacy suffix for clocks used by MSM DRM driver.
The _clk suffix has been deprecated since commit 20c3bb80235 ("drm/msm:
drop _clk suffix from clk names").
Fixes: 720c3bb80235 (drm/msm: drop _clk suffix from clk names)
The following warnings during boot have been seen since the referenced
fixes commit:
msm_dsi_phy 1a98300.dsi-phy: Using legacy clk name binding. Use "iface" instead of "iface_clk"
msm 1a00000.mdss: Using legacy clk name binding. Use "iface" instead of "iface_clk"
msm 1a00000.mdss: Using legacy clk name binding. Use "bus" instead of "bus_clk"
msm 1a00000.mdss: Using legacy clk name binding. Use "vsync" instead of "vsync_clk"
msm_mdp 1a01000.mdp: Using legacy clk name binding. Use "bus" instead of "bus_clk"
msm_mdp 1a01000.mdp: Using legacy clk name binding. Use "iface" instead of "iface_clk"
msm_mdp 1a01000.mdp: Using legacy clk name binding. Use "core" instead of "core_clk"
msm_mdp 1a01000.mdp: Using legacy clk name binding. Use "vsync" instead of "vsync_clk"
msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "mdp_core" instead of "mdp_core_clk"
msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "iface" instead of "iface_clk"
msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "bus" instead of "bus_clk"
msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "byte" instead of "byte_clk"
msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "pixel" instead of "pixel_clk"
msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "core" instead of "core_clk"
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Nicolas Dechesne <nicolas.dechesne@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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The ETF input should be connected to the funnel output, and the ETF
output should be connected to the replicator input. The labels are wrong
and these got swapped:
Warning (graph_endpoint): /soc/funnel@821000/ports/port@8/endpoint: graph connection to node '/soc/etf@825000/ports/port@1/endpoint' is not bidirectional
Warning (graph_endpoint): /soc/replicator@824000/ports/port@2/endpoint: graph connection to node '/soc/etf@825000/ports/port@0/endpoint' is not bidirectional
Fixes: 7c10da373698 ("arm64: dts: qcom: Add msm8916 CoreSight components")
Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Remove the usage of IRQ_TYPE_NONE to fix loud warnings from
patch (83a86fbb5b56b "irqchip/gic: Loudly complain about
the use of IRQ_TYPE_NONE").
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Thierry Escande <thierry.escande@linaro.org>
Tested-by: Thierry Escande <thierry.escande@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add cpu cooling maps for cpu passive trip points. The cpu cooling
device states are mapped to cpufreq based scaling frequencies.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add a CPU OPP table to allow CPU frequency scaling on msm8916 platforms.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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There are clock controller registers in the APCS block, which purpose
is to control the main CPU mux and divider. Add the clock properties as
part of the APCS device-tree node.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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The APCS block was exposed until now as a syscon, but now we have a
proper driver for this block. Add the compatible string of the new
driver to probe and register the mailbox functionality.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add a device tree node for the A53 PLL, which exists on msm8916
platforms.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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The QUP core can be used either for I2C or SPI, so the same IP is mapped
by a driver or the other. SPI bindings use a leading 0 for the start
address and a size of 0x600, I2C bindings don't have the leading 0 and
have a size 0x1000.
To make them more similar, add the leading 0 to I2C bindings and changes
the size to 0x500 for all of them, as this is the actual size of these
blocks. Also align the second entry of the clocks array.
Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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SMSM is not symmetrical, the incoming bits from WCNSS are available at
index 6, but the outgoing host id for WCNSS is 3. Further more, upstream
references the base of APCS (in contrast to downstream), so the register
offset of 8 must be included.
Fixes: 1fb47e0a9ba4 ("arm64: dts: qcom: msm8916: Add smsm and smp2p nodes")
Cc: stable@vger.kernel.org
Reported-by: Ramon Fried <rfried@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add a missing #phy-cells to the dsi-phy, to silence dtc warning.
Cc: Archit Taneja <architt@codeaurora.org>
Fixes: 305410ffd1b2 ("arm64: dts: msm8916: Add display support")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/soc
Pull "Qualcomm ARM64 Updates for v4.15" from Andy Gross:
* Add PCIE support to relevant MSM8996 based boards
* Add RPM clock controller node on MSM8996
* Add dload address on MSM8916 and MSM8996
* Add MBHC button support on APQ8016 SBC
* Add RTMFS specific compatible for rmtfs memory node
* Fixups for MSM8916 GPIO line names and MDP address length
* tag 'qcom-arm64-for-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: msm8916: Mark rmtfs node as qcom, rmtfs-mem compatible
arm64: dts: msm8996: Add the rpm clock controller node
arm64: dts: qcom: sbc: Name GPIO lines
arm64: dts: qcom: msm8916: Shrink mdp address length for msm8916
arm64: dts: apq8016-sbc: add mbhc buttons support
arm64: dts: qcom: Specify dload address for msm8916 and msm8996
arm64: dts: apq8096-db820c: never disable regulator on LS expansion
arm64: dts: apq8096-db820c: Enable on board 3 pcie root complex
arm64: dts: qcom: msm8996: add support to pcie
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Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using
the following command:
perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm64/boot/dts -type -f -name '*.dts*'
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Now that we have a binding defined for the shared file system memory use
this to describe the rmtfs memory region.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This shrinks the address size down to 89000 from its previous 90000
which was mistakenly pulled from downstream.
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
Acked-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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On msm8916 and msm8996 boards a secure io-write is used to write the
magic for selecting "download mode", specify this address in the
DeviceTree.
Note that qcom_scm.download_mode=1 must be specified on the kernel
command line for the kernel to attempt selecting download mode.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This patch adds the IOMMU node for the IOMMU that resides on the
Qualcomm MSM8916 platforms.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This patch adds the Qualcomm Venus video codec node for the video
codec hardware residing on MSM8916 platforms.
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This patch adds the Qualcomm Adreno GPU node that exists in the
MSM8916.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Replace the obsolete compatible string for Coresight programmable
replicator with the new one.
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann:
"Device-tree updates for arm64 platforms. For the first time I can
remember, this is actually larger than the corresponding branch for
32-bit platforms overall, though that has more individual changes.
A significant portion this time is due to added machine support:
- Initial support for the Realtek RTD1295 SoC, along with the Zidoo
X9S set-top-box
- Initial support for Actions Semi S900 and the Bubblegum-96
single-board-cёmputer.
- Rockchips support for the rk3399-Firefly single-board-computer gets
added, this one stands out for being relatively fast, affordable
and well₋supported, compared to many boards that only fall into one
or two of the above categories.
- Mediatek gains support for the mt6797 mobile-phone SoC platform and
corresponding evaluation board.
- Amlogic board support gets added for the NanoPi K2 and S905x
LibreTech CC single-board computers and the R-Box Pro set-top-box
- Allwinner board support gets added for the OrangePi Win, Orangepi
Zero Plus 2, NanoPi NEO2 and Orange Pi Prime single board computers
and the SoPine system-on-module.
- Renesas board support for Salvator-XS and H3ULCB automotive
development systems.
- Socionext Uniphier board support for LD11-global and LD20-global,
whatever those may be.
- Broadcom adds support for the new Stingray communication processor
in its iProc family, along with two reference boards.
Other updates include:
- For the hisicon platform, support for Hi3660-Hikey960 gets extended
significantly.
- Lots of smaller updates for Renesas, Amlogic, Rockchip, UniPhier,
Broadcom, Allwinner, Hisilicon, Qualcomm, Marvell, and NXP"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (243 commits)
ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
Revert "arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k"
arm64: dts: mediatek: don't include missing file
ARM64: dts: meson-gxl: Add Libre Technology CC support
dt-bindings: arm: amlogic: Add Libre Technology CC board
dt-bindings: add Libre Technology vendor prefix
arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K
arm64: dts: zte: Use - instead of @ for DT OPP entries
arm64: dts: marvell: add gpio support for Armada 7K/8K
arm64: dts: marvell: add pinctrl support for Armada 7K/8K
arm64: dts: marvell: use new binding for the system controller on cp110
arm64: dts: marvell: remove *-clock-output-names on cp110
arm64: dts: marvell: use new bindings for xor clocks on ap806
arm64: dts: marvell: mcbin: enable the mdio node
arm64: dts: Add Actions Semi S900 and Bubblegum-96
dt-bindings: Add vendor prefix for uCRobotics
arm64: dts: marvell: add xmdio nodes for 7k/8k
arm64: dts: marvell: add a comment on the cp110 slave node status
arm64: dts: marvell: remove cpm crypto nodes from dts files
arm64: dts: marvell: cp110: enable the crypto engine at the SoC level
...
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Add debug unit on Qualcomm msm8916 based platforms, including the
DragonBoard 410c board.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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We currently have three device nodes for the same USB hardware
block, as evident by the reuse of the same reg address multiple
times. Now that the chipidea driver fully supports OTG with the
MSM wrapper we can collapse all these nodes into one USB device
node, reflecting the true nature of the hardware.
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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