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bug 829399 - enable front sensor of enterprise board
Change-Id: I4d0753d7f82e538cc133dc680924b59a46a9ea82
Reviewed-on: http://git-master/r/39002
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
Tested-by: Jeremy Wyman <jwyman@nvidia.com>
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bug 829399 - add front camera ov9726
Change-Id: Iea0db38d3d2a55acf89e9e49a870ecfc4ad0e109
Reviewed-on: http://git-master/r/39003
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Tested-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Chonglei Huang <chahuang@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
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Change-Id: Ifd9d1de52b4859ec16d82287c0944798b6c98d10
Reviewed-on: http://git-master/r/39267
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
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Set the default sleep mode to be lp0.
Note: This change only affects Tegra3-A02. For A01, the default sleep mode is
still lp1.
Bug 802410
Change-Id: Ie9c38333a1048562569333f74bd743960f446ea2
Reviewed-on: http://git-master/r/38780
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
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Since clock is required when resetting devices, always enable pllc and plla at
the beginning of clock restore routine.
Change-Id: Ib634408f23677ce1cf629576130bbc5a6ca767af
Reviewed-on: http://git-master/r/38778
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
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governor swithing is causing the system to fail on LP0 resume. Disable it for
now.
DO NOT merge back to main.
Change-Id: Id2ffcbd9657b8abff7c943e1d62e16b4a14e0b42
Reviewed-on: http://git-master/r/38853
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
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By defalut PCIE and SATA partitions are powergated. If needed,
respective drivers should un-powergate these partitions.
Change-Id: Ibe2ada3e8b9738393140ad3dbbd7af4a9d94e889
Reviewed-on: http://git-master/r/38816
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Tested-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
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This change provides a centralized location for powergating modules.
It would take care of switching on/off clocks while un-powergating/
powergating modules respectively.
Bug: 814267
Change-Id: Ia25cf38d2f1e6df1ee0e1a6d8f46b9674a5ed24b
Reviewed-on: http://git-master/r/38815
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Tested-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
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DO NO INTEGRATE INTO MAIN
Enable rear camera sensor for enterprise board
Change-Id: I3f17a719933a9914ecfd68368e469ab3f07c2188
Reviewed-on: http://git-master/r/38751
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Tested-by: Jihoon Bang <jbang@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
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DO NOT INTEGRATE INTO MAIN
Add and enable rear camera sensor.
Support only one sensor for now.
Change-Id: Ifb9e15d0061a8547f0b3afd347bf0f11b26970c4
Reviewed-on: http://git-master/r/38752
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Tested-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
Tested-by: Jeremy Wyman <jwyman@nvidia.com>
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Change-Id: I321a7346741dfc0a932d3fd6b5d14bb0d9b63cc5
Reviewed-on: http://git-master/r/39025
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
Tested-by: Jeremy Wyman <jwyman@nvidia.com>
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Regulator disable in postsuspend cause suspend/resume break.
Bug 841104
Change-Id: I67962d51b97ef9775e31c2b2c4b977a77895ed05
Reviewed-on: http://git-master/r/39024
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
Tested-by: Jeremy Wyman <jwyman@nvidia.com>
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Adding VBUS regulator information to activate the VBUS.
bug 833736
Change-Id: Icfd81e73d654c459e7d001857857343a715a056e
Reviewed-on: http://git-master/r/39023
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
Tested-by: Jeremy Wyman <jwyman@nvidia.com>
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Updated SDRAM emc clock table for below freqs.
25.5 MHz, 51 MHz, 102 MHz, 400 MHz.
Bug 832436
Change-Id: I8069a82cb504dbd9a530f5a09238e0faf39722a9
Reviewed-on: http://git-master/r/39020
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
Tested-by: Jeremy Wyman <jwyman@nvidia.com>
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Bug 829405
Change-Id: Ie78d245a99013fa09968443aa3358049f2e97c55
Reviewed-on: http://git-master/r/39019
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
Tested-by: Jeremy Wyman <jwyman@nvidia.com>
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Added AVP clock control using Tegra3 activity monitoring device.
The target AVP frequency floor is set based on average load and
short term boost. Average AVP load time (time when AVP is not
halted by flow controller) is determined by fixed frequency count
provided by monitoring h/w featuring 1st order IIR activity filter.
The boost frequency is calculated by s/w - exponentially increasing/
decreasing when sampled AVP activity has crossed upper/lower boost
watermarks.
The implementation is interrupt driven - periodic sampling is hidden
by h/w. The tune-able debugfs parameters are:
/sys/kernel/debug/tegra_actmon/avp/boost_step - boost rate increase
step (% of max AVP frequency)
/sys/kernel/debug/tegra_actmon/avp/boost_rate_inc - boost rate
increase factor (%)
/sys/kernel/debug/tegra_actmon/avp/boost_rate_dec - boost rate
decrease factor (%)
/sys/kernel/debug/tegra_actmon/avp/boost_threshold_up - upper
activity watermark for boost increase (AVP active time in %)
/sys/kernel/debug/tegra_actmon/avp/boost_threshold_dn - lower
activity watermark for boost decrease (AVP active time in %)
Change-Id: Ia82247176531f2fb67acfc277e63b9f16916a488
Reviewed-on: http://git-master/r/37175
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Added EMC clock control using Tegra3 activity monitoring device.
The target EMC frequency floor is set based on average activity
and short term boost. Average EMC activity is obtained directly
from monitoring h/w featuring 1st order IIR activity filter. The
boost frequency is calculated by s/w - exponentially increasing/
decreasing when sampled EMC activity has crossed upper/lower boost
watermarks.
The implementation is interrupt driven - periodic sampling is hidden
by h/w. The tune-able debugfs parameters are:
/sys/kernel/debug/tegra_actmon/emc/boost_step - boost rate increase
step (% of max EMC frequency)
/sys/kernel/debug/tegra_actmon/emc/boost_rate_inc - boost rate
increase factor (%)
/sys/kernel/debug/tegra_actmon/emc/boost_rate_dec - boost rate
decrease factor (%)
/sys/kernel/debug/tegra_actmon/emc/boost_threshold_up - upper
activity watermark for boost increase (% of current EMC frequency)
/sys/kernel/debug/tegra_actmon/emc/boost_threshold_dn - lower
activity watermark for boost decrease (% of current EMC frequency)
Change-Id: I385c6e0a75da42dada792db6b4018b68fea8f23b
Reviewed-on: http://git-master/r/36790
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Enable new Atmel touch driver with early suspend/resume.
BUG 826854
Change-Id: I732d9322aab35baf1b97f8f86dbd31b79a3dad85
Reviewed-on: http://git-master/r/34975
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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* Update board files for new Atmel MaxTouch driver.
* Fix section mismatch with touch init (merged from other commit)
- Mark the tegra_touchscreen_init structures as __initdata,
since theycan be dropped once initialization has completed.
- Mark generic_touch_init() as __init, since it is only called from
the init path of various boards.
BUG 826854
Change-Id: Ifa73d89f8f62d2ac5b1e646276e444f87274d38f
Reviewed-on: http://git-master/r/35287
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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If the screen is idle (no POST for some time), reduce the DC EMC clock
according the windows size. If external display connected, the EMC clock
will not be reduced.
BUG 828306
Change-Id: I6fb62ce6baf3380737c76b71f16e38ad6465a667
Reviewed-on: http://git-master/r/37106
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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tegra_dc_hdmi_equal doesn't check pixclock and some devices doesn't
support 148.5Mhz pixclock which is needed for 1080p@60. However,
adding 1080p@30 to the supported hdmi mode array makes
tegra_dc_hdmi_equal to retun 1080p@60. Therefore, this commit adds
max pixclock check to distinguish modes with different pixclock
Bug: 815409
Change-Id: Ifbf07929e3c7a92172856518a55e9d4a04f0b943
Reviewed-on: http://git-master/r/32511
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Change-Id: I55f52ab038764079811c68b3bb3738a9de17d7bf
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/31530
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Giving read-write permission for user only for sysfs attributes.
Group and other will have only read permission.
- tegra_mc_stats: enable and quantum
- susend: mode
- clock: rate, parent, state
File System Permission CTS expects this to pass.
Bug 840409
Change-Id: I3335b27124be38f0f5ea4cc415fef6532e574680
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/36867
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Reviewed-on: http://git-master/r/30512
(cherry picked from commit 52e7d11bc42abb7643191bccf55fc9fc66b640d2)
Change-Id: I35c6e91dc943637fdebb0db1a633c5bc1c39727f
Reviewed-on: http://git-master/r/31112
Tested-by: Manjula Gupta <magupta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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disable_irq() will do schedule() if threaded IRQ handler is running. But
suspend_cpu_complex() is called from IRQ disabled.
disable_irq_nosync() should be used here because it will not sleep.
BUG 841808
Change-Id: Id6cfd8c1ad305281422da878ae77b93b58f3b306
Reviewed-on: http://git-master/r/37505
Reviewed-by: Xin Xie <xxie@nvidia.com>
Tested-by: Xin Xie <xxie@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Enterprise uses digital microphone. This change allows max98088
to enable clock for microphone input.
Bug 840691
Change-Id: Ia1695c9a7d9d69eb9944b9f6819ec78fd7dbe518
Reviewed-on: http://git-master/r/37945
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Tested-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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For sh532u, when regulator_get fails, it still returns
unwanted value. Reset regulator variable to NULL and
return error.
bug 841078
Change-Id: I7265b2b5ca40405c92555a242d7d39f5dfe2bb07
Reviewed-on: http://git-master/r/37848
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
Tested-by: Prayas Mohanty <pmohanty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Enable PMU only features for LP0. System-wise LP0 is not enable by default yet.
1. Allow pmu SLEEP state
2. Keep 32KHz clk out from PMU enabled on LP0
3. Set core_power_req to be high enable
4. Turn off VDD1 (power for Vcore) on LP0
Change-Id: Id6babdfc36de1a597f8df5d2943ef048699013d4
Reviewed-on: http://git-master/r/32853
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Change-Id: Ia631f7bae013f378c36fe05c665ef178bef12a46
Reviewed-on: http://git-master/r/31904
Reviewed-by: Kevin Huang <kevinh@nvidia.com>
Tested-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
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Change-Id: I97434334a4214180a365d9709a331405da135669
Reviewed-on: http://git-master/r/36202
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
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Remove executable permission from source files.
Change-Id: I174be22b3b753569e33de1dc1fed2e823fda6120
Reviewed-on: http://git-master/r/37956
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
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Board changes needed to enable TI PMU 80031 RTC
on enterprise are added.
bug 833336
Change-Id: Ic2d2374ed6bff773964bd7bf6b81c69feda2d9b1
Reviewed-on: http://git-master/r/34457
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Enabling PMU 80031 RTC config variable in the enterprise defconfig
bug 833336
Change-Id: Ia4ee9c91ac47ef9b4ae3e0260fa17d67a7a78451
Reviewed-on: http://git-master/r/34455
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Adding uart platform data for the hsuart driver. Passing the
clock information through the platform data.
bug 837140
bug 836059
Change-Id: I321cd904ea072b0bc931016d46a4fa8462c28c8d
Reviewed-on: http://git-master/r/37636
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Board related changes, needed to turn off the device,
are being addded.
bug 833661
Change-Id: Ia5f5f69fc19367995e6ad988a185825bd7b4d969
Reviewed-on: http://git-master/r/36670
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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This reverts commit 9d8f88a186320e9eb032059ae101cccd5e66781b.
Original change broke LP1 suspend/resume
Bug 840959,841139
Change-Id: I03bcf98bbe8fc397b27be8d45f4658ef0ecc4d43
Reviewed-on: http://git-master/r/37354
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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The PMU generates interrupt as active low. So configuring the
Power management unit to have the active low interrupt from PMU_INT
pin.
bug 839238
Change-Id: I69e5cfb756d3b9e39fe7515cf8126753800cda03
Reviewed-on: http://git-master/r/37670
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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change the input supply to master 5v to enable VDDIO_HDMI
signal for HDMI.
Bug 825778
Bug 823160
Change-Id: I2d6360ab3769ff876bdb7d0e0b34d9298aa780d0
Reviewed-on: http://git-master/r/35904
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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1. The usb UTMIP controllers are set to reset mode when there is no usb cable.
2. Power down the reciever circuitory.
3. Set the OTG_PD for instances which do not use OTG.
Bug 829628
Change-Id: I90b5c4aad30cf29ab4817aa3479fa323a20699bc
Reviewed-on: http://git-master/r/35894
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
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3D hardware workaround is needed for Tegra3 A01 only. With this patch, we
read run-time whether it should be enabled or not.
Workaround should be removed once A01's have been phased out.
Bug 786316
Change-Id: Icd1b85b30a53c74d2e5c7a6df65a805d1fe5147c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/32136
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Gpio controlling w_disable has changed since Fab3.
Modify it accordingly.
Bug 819563
Change-Id: Idbeb9467168aa91c5cf942f72ec5d581a28dc4d1
Reviewed-on: http://git-master/r/36368
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Added power rails and driver registration for harmony.
Also registering power off function to power off machine.
Change-Id: I3708e798cb128755574510737032a46624f8822f
Reviewed-on: http://git-master/r/35878
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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On Tegra3 clocks of major h/w engines - 2D/EPP/3D/MPE/VDE/SE - are
sourced from PLLC through integer dividers. Low resolution of these
dividers does not allow to set scaling frequency levels matching
intermediate voltage steps within core voltage range. Only changing
the source frequency can achieve it. However, re-locking common PLL
while engines are running requires synchronization of engines clock
control, and complex operations including switching to backup sources
during PLL stabilization time.
This commit introduces a new virtual clock "cbus" to support clocks
synchronization and PLLC re-locking procedures. The dvfs table for
cbus clock is constructed from frequency steps close to maximum rates
for each characterized core voltage level. Engine clocks exposed to
the drivers are no longer physical module clocks, but shared cbus
users. Setting the rate for such clock specifies the clock floor.
The final cbus rate is determined as maximum floor setting for all
enabled engines, and rounded up along the cbus dvfs ladder. Actual
engine clock rate is set equal to the cbus clock rate. Hence, engines
will be running close to maximum frequency for minimum voltage that
satisfies all floor requests.
Special case: Host1x. This clock will be always configured at 1/2 of
cbus clock rate, and its shared user floor request is ignored by cbus
target frequency calculations.
Added cbus dvfs tables and updated VDE engine dvfs data.
Change-Id: Ic02ea08227f920dc4f47b2389c311a23cea472f6
Reviewed-on: http://git-master/r/36199
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Adding setup function for the kernel command option pmuboard.
bug 829846
Change-Id: I227fcab7b805a50945dc39a193ba29d90663b9f8
Reviewed-on: http://git-master/r/36557
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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The core_pwr_req signal need to be make high for the PMU A03 and A04.
bug 829846
Change-Id: Ie568a29e76823e86743893ea59953b0429cc027a
Reviewed-on: http://git-master/r/36544
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Bug 820602
Reviewed-on: http://git-master/r/35954
(cherry picked from commit 2d6cac283c1121b9a90b742b5dcf80141422eac6)
Change-Id: I87f725e1d5d90f95157f6bf9e886b415aeccb21f
Reviewed-on: http://git-master/r/36688
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Cho-Che Cheng <jacheng@nvidia.com>
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Change-Id: I0c19d71935a2c84ab51c0e2dcb5277670e1f96f8
Reviewed-on: http://git-master/r/35926
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
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Adding config variable for enabling INA219 power monitor.
bug 808311
Change-Id: Ib2d59b14974f30643baf71ade01805f8043aee14
Reviewed-on: http://git-master/r/34300
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Board details needed by INA219 power monitor device
to measure current, voltage and power on Cardhu are
being filled.
bug 808311
Change-Id: Idbee6034312f5bd888b1ed87ef98f531c45938a0
Reviewed-on: http://git-master/r/34299
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Change-Id: I07aa6bfdbbb12f7e921f1f1be7136dae8bd8a834
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