| Age | Commit message (Collapse) | Author |
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It is not working correct
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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To allocate memory for the GPU we need the RAM size.
We can choose the ramsize over the Kernelkonfig.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Change display eeprom address to 0x50, which is default.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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For the DL we need a delay on the RX lines. Without the delay
we loos all packages.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Add support for duallite and single core version of i.MX6 CPU
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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On some modules SATA don't work if pcie disable the SATA clock.
Remove the SATA clock from pcie clock tree and enable SATA clock before the
pcie clock.
PCIe needs the SATA clock:
/*
* Enable SATA ref clock.
* PCIe needs both sides to have the same source of refernce clock,
* The SATA reference clock is taken out to link partner.
*/
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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The busfreq function support is in the kernel since:
commit 32ea8aa56866047e100c6600cf663aaf786d8dbe
Author: Ranjani Vaidyanathan <ra5478@freescale.com>
Date: Tue Feb 7 14:34:13 2012 -0600
|ENGR00179574: MX6- Add bus frequency scaling support
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|Add support for scaling the bus frequency (both DDR
|and ahb_clk).
|The DDR and AHB_CLK are dropped to 24MHz when all devices
|that need high AHB frequency are disabled and the CORE
|frequency is at the lowest setpoint.
|The DDR is dropped to 400MHz for the video playback usecase.
|In this mode the GPU, FEC, SATA etc are disabled.
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|To scale the bus frequency, its necessary that all cores
|except the core that is executing the DDR frequency change
|are in WFE. This is achieved by generating interrupts on
|un-used interrupts (Int no 139, 144, 145 and 146).
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|Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Add freescale SATA platform changes to phyFLEX-i.MX6
|ENGR00243339 imx: sata: disable sata phy when sata is not enabled
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|In order to save power consumption, disable sata phy
|(enable PDDQ mode) in kernel level, if the sata module
|is not enabled in kernel configuration.
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|Signed-off-by: Richard Zhu <r65037@freescale.com>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Remove not needed code from ethernet phy init
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Module revison 2 has some changes compared to revision 1.
NAND:
- disconnected NAND_D8-D15 because only 8-Bit NAND is supported by i.MX 6
- connected NANDF_DQS (SD4_DAT0) to NAND-Flash to support sync. mode
PMIC:
- Moved PMIC_nIRQ from DI0_PIN15 to SD4_DAT1
PCIe:
- Added nPCIe0_PERST to pad DI0_PIN15 (GPIO4_17)
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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That we can change the values of the structs revisions depending
the structs can't be const.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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The pin SD4_DAT4 until SD4_DAT7 be used as revison control.
The pins will be internel pulled up so we read a 1111 for revison 1.
For revison two the first pin (bit) is pulled down (see schematic pfla-02
page 4 "SDIO, NAND-Flash".
On Module rev 1 the pins are connectet to the NAND but we have only 8bit NAND
also the i.MX6 only can handle 8bit NAND flashs.
Revisions:
Rev 1: 0xF
Rev 2: 0xE
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Rev 15: 0x1
Rev 16: 0x0
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Fix cam selection typo, the cam name is tw9910
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Change the frequencies for the pll4 (clock.c)
Change the frequencies for the different phytec camera moduls (board-mx6q_phyflex.c)
Add new pll configs for the mt9p031 sensor (mt9p031.c)
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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This is not need in the platform code.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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This is only a workarround to fix bootproblems with i.MX6.
Sometimes the kernel dosn't boot and print the message
"COULD NOT SET GP VOLTAGE".
With the delay it look likes the kernel boot correct.
For more informations look at:
https://community.freescale.com/message/319514#319514
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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If didn't set the param ldo_active param in command line we use LDO_MODE_BYPASS
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Andrei Andreyanau <a.andreyanau@sam-solutions.com>
modified: arch/arm/mach-mx6/board-mx6q_phyflex.c
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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New bootargs added
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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clko2
Signed-off-by: Andrei Andreyanau <a.andreyanau@sam-solutions.com>
modified: arch/arm/mach-mx6/board-mx6q_phyflex.h
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Andrei Andreyanau <a.andreyanau@sam-solutions.com>
modified: arch/arm/mach-mx6/board-mx6q_phyflex.c
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Andrei Andreyanau <a.andreyanau@sam-solutions.com>
modified: arch/arm/mach-mx6/board-mx6q_phytec-nand.c
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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clko2_clk parent clock source.
Signed-off-by: Andrei Andreyanau <a.andreyanau@sam-solutions.com>
modified: arch/arm/mach-mx6/clock.c
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Uladzimir Bely <u.bely@sam-solutions.net>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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particular 'power' button)
Signed-off-by: Uladzimir Bely <u.bely@sam-solutions.net>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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dividers for 26MHz clock source and 48/96MHz PCLK for mt9p031 camera.
modified: arch/arm/mach-mx6/board-mx6q_phyflex.c
modified: drivers/media/video/mt9p031.c
Signed-off-by: Uladzimir Bely <u.bely@sam-solutions.net>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Added support for at24c04 eeprom with 512 bytes (page write up to 16
bytes per cycle). Accessible at i2c address 0x52.
Signed-off-by: Uladzimir Bely <u.bely@sam-solutions.net>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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For led control pca9538 is used. Currently both green and red leds are
on for selected video input.
Signed-off-by: Uladzimir Bely <u.bely@sam-solutions.net>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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added support for selecting target frequency for MT9P031 camera. modified: arch/arm/mach-mx6/board-mx6q_phyflex.c modified: arch/arm/plat-mxc/include/mach/mxc_camera.h
Signed-off-by: Uladzimir Bely <u.bely@sam-solutions.net>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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* soc_camera driver now tries to call enum_input, g_input and s_input
handlers from host camera driver if such exists;
* tw9910 v4l device type redefined from V4L2_INPUT_TYPE_TUNER to
V4L2_INPUT_TYPE_CAMERA;
* added basic implementation of g_input and s_input for managing
current videoinput handlers to tw9910 driver;
Note: currently deinterlacing is disabled by default in the mxc_ipu
driver so tw9910 returns interlaced image. Deinterlacing mode can be
hardcoded on in the csi_enc_setup(struct mxc_camera_dev *cam) from
drivers/media/video/mxc_ipu_csi_enc.c.
Signed-off-by: Uladzimir Bely <u.bely@sam-solutions.net>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Set the reset GPIO for pcie correct
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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With rev .1 the WP GPIO is GPIO_1_29.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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To enable ubs1 we must mux GPIO0 as gpio an set to high
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Set the reset GPIO for pcie correct
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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GPIO PAD NR
0 MX6Q_PAD_DISP0_DAT14__GPIO_5_8 136
1 MX6Q_PAD_DISP0_DAT13__GPIO_5_7 135
2 MX6Q_PAD_DI0_PIN2__GPIO_4_18 114
3 MX6Q_PAD_DI0_PIN3__GPIO_4_19 115
4 MX6Q_PAD_GPIO_6__GPIO_1_6 6
5 MX6Q_PAD_GPIO_9__GPIO_1_9 9
6 MX6Q_PAD_GPIO_17__GPIO_7_12 204
7 MX6Q_PAD_GPIO_18__GPIO_7_13 205
8 MX6Q_PAD_GPIO_19__GPIO_4_5 101
9 MX6Q_PAD_EIM_CS0__GPIO_2_23 55
10 MX6Q_PAD_EIM_CS1__GPIO_2_24 56
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Since phyFLEX Carrier-Board rev .2 we have not longer PEBs
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Remove the SPI NOR partions from boardfile.
The partions will set in the barebox and transfer to the kernel with bootargs.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Add to another patch
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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The partition info will added over bootargs
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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avoids calling ldb_disp_init twice when the display is duplicated.
this gets rid of the error message:
mxc_ldb mxc_ldb: for second ldb displdb mode should in separate mode
mxc_sdc_fb mxc_sdc_fb.1: NO mxc display driver found!
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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appearently the dallas 1-wire stuff is using it, leftover from the
conversion from .0 to .1
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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