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2010-10-12[ARM] tegra: ventana: add graphics supportGary King
register the tegradc0, tegradc1, grhost, pwm-backlight and carveout devices Change-Id: Ia61c0632470e571cc57279dc3b197ccd1fca80f0 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-12[ARM] tegra: ventana: add ldo3 consumer for avdd_lvdsGary King
Change-Id: If5e07b2eb62805a00426799184989fa290318f4a Signed-off-by: Gary King <gking@nvidia.com>
2010-10-12[ARM] tegra: ventana: remove BUG() in set_charge.Gary King
Signed-off-by: Gary King <gking@nvidia.com>
2010-10-12Revert "[ARM] mmu: add option to map lowmem with page mappings"Rebecca Schultz Zavin
This reverts commit ac21b321048091bdbf45bbda87161cc9f312c393.
2010-10-12[ARM] attrib_alloc: fix outer cache flush end addressGary King
when allocating uncached pages, the outer cache should be flushed; the end address should be specified in bytes, not in pages. Change-Id: I3fe036f4f7e10e009f96567e3afeeef6ea603240 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-12Revert "video: tegra: add utility function to compute framebuffer stride"Erik Gilling
This reverts commit 10c751b8f5bb78f674d4939b47be933934bb23dd. Change-Id: I236ddcd531d3ca17c8727cac84e6d2aa6e27dbe1
2010-10-12video: tegra: clean up fb flipping codeErik Gilling
Signed-off-by: Erik Gilling <konkers@android.com> Change-Id: I1c1f5aea92c1b062c8ccf2f2f6116c399d847262
2010-10-12[ARM] tegra: add 10us delay after unclamping in powergate_on sequenceErik Gilling
Signed-off-by: Erik Gilling <konkers@android.com> Change-Id: I94a979e6a1ec6ecf80b4d4f1721a8aacac7b8a11
2010-10-08video: tegra: add host1x support to driverGary King
includes changes by: Antti Hatala <ahatala@nvidia.com> (1) Gary King <gking@nvidia.com> (1) Erik Gilling <konkers@android.com> (2) Antti Hatala <ahatala@nvidia.com> video: tegra: dc: use nvhost driver for host1x power management Gary King <gking@nvidia.com> video: tegra: fb: add ioctl to flip dc windows to nvmap handles Erik Gilling <konkers@android.com> video: tegra: dc: increment syncpoints following window flips video: tegra: drain syncpt waits on display disable Original commit messages: ** video: tegra: dc: use nvhost driver for host1x power management Incrementing the frame done syncpoint value from the display interrupt requires that the host module is powered on. As the syncpoint state is saved and restored automatically by the host driver a cpu increment of a syncpoint in the powered down state will be lost. Also adds checks for host module being powered. ** video: tegra: fb: add ioctl to flip dc windows to nvmap handles tegra user-space graphics drivers may allocate framebuffers using nvmap rather than rendering to the common framebuffer, this may be done to support deeper buffer pipelining, color formats and pixel layouts other than the initial bootup framebuffer, etc. to use this ioctl, a caller must first specify an nvmap fd which is already open in the calling process so that the subsequent flip ioctls may be properly validated. flips are performed asynchronously, with flip completion notifications provided back to the caller via the host1x syncpoint mechanism based on earlier changes made by Antti Hatala <ahatala@nvidia.com> and Erik Gilling <konkers@android.com> Change-Id: I4e8a8bb92085a485d65fd87d89112b2969ee37ff Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08[ARM] tegra: add graphics host to devices.cGary King
Change-Id: I4c694d3c9f8a15975591ba5b61625da410991efd Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08[ARM] tegra: add SYNCPT_THRESH interrupts to irqs.hGary King
Change-Id: Ibff6f3281b6e81143b5f4535d6d5688e6a631b46 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08[ARM] tegra: add graphics host apertures to iomap.hGary King
Change-Id: Ic6acf37bdc36aaa8af71bd2a576089ca8579fcc6 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08video: tegra: host1x driverGary King
the graphics and display hardware on tegra SoCs is accessed through a command DMA front-end called host1x host driver clients place commands into memory objects called streams, and submit a stream on one of 8 channels: the assignment of streams-to-channels depends on the hardware module(s) programmed by the stream: for example, all streams which program the 3D hardware are submitted on channel 1. the host1x hardware includes two synchronization primitives to allow command streams to synchronize access to memory or to hardware engines shared across channels (e.g. the 2D blitter): sync points and module mutexes. both primitives can also be used to synchronize with the CPU. the host1x driver performs power management for all modules behind the host block: once a module is idle (i.e., the last stream which accesses it has completed, indicated by a syncpoint) and has remained idle for an extended period of time, the module's clock (and power gate island, if the module is uniquely power-gated) is disabled, and will be automatically re-enabled when a new stream is submitted for that module. includes channel debugging support originally implemented by Erik Gilling <konkers@google.com> Original Author: Antti Hatala <ahatala@nvidia.com> Signed-off-by: Gary King <gking@nvidia.com> Change-Id: Idf0ecc8e7710f3839903a9fbfbe5650990a96b2c
2010-10-08video: tegra: add utility function to compute framebuffer strideGary King
framebuffers will generally not be exactly width * bpp / 8 bytes wide; on tegra, linearly-addressed framebuffers will generally be rounded up so that the stride is a multiple of 16B (so that they are compatible with rendering from the hardware engines), and tiled framebuffers will be a multiple of the tile width (64B). add a utility function to tegra_dc to compute the correct stride given a width, bpp and pixel layout, and use this in set_par. Change-Id: I803a55b49c12476f20d5644707899c3fe1336c2d Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08video: tegra: move nvhost.h to mach-tegra/include/nvhost.hGary King
Change-Id: I3bcc0a91cb379c0bd6ef382a5bf10e2406e55697 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08video: tegra: add GPU memory management driver (nvmap)Gary King
nvmap provides an interface for user- and kernel-space clients to allocate and access memory "handles" which can be pinned to enable the memory to be shared with DMA devices on the system, and may also be mapped (using caller-specified cache attributes) so that they are directly accessible by the CPU. the memory handle object gives clients a common API to allocate from multiple types of memory: platform-reserved physically contiguous "carveout" memory, physically contiguous (order > 0) OS pages, or physically discontiguous order-0 OS pages that can be remapped into a contiguous region of the DMA device's virtual address space through the tegra IOVMM subsystem. unpinned and unmapped memory handles are relocatable at run-time by the nvmap system. handles may also be shared between multiple clients, allowing (for example) a window manager and its client applications to directly share framebuffers Change-Id: Ie8ead17fe7ab64f1c27d922b1b494f2487a478b6 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08[ARM] tegra: mirror inner-cacheable change in tegra startupGary King
Change-Id: Ibe2662934076a28a6ce22ffc5eb0bfaa46f98ccd Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08[ARM] mm: add memory type for inner-writebackGary King
For streaming-style operations (e.g., software rendering of graphics surfaces shared with non-coherent DMA devices), the cost of performing L2 cache maintenance can exceed the benefit of having the larger cache (this is particularly true for OUTER_CACHE configurations like the ARM PL2x0). This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) in the tex remapping tables as an inner-writeback-write-allocate, outer non-cacheable memory type, so that this mapping will be available to clients which will benefit from the reduced L2 maintenance. Change-Id: Iaec3314a304eab2215100d991b1e880b676ac906 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08[ARM] tegra: change SMP startup to use read-allocate cacheGary King
mirror the change to v7 common startup in the tegra-specific LP2 and hotplug statup routines Change-Id: I0552eba951dbfc168e37e59b41394d31fab30256 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08[ARM] mm: change to read-allocate as default SMP cache policyGary King
the "streaming" mode optimization which skips cacheline allocation for fully-dirty lines is frequently defeated when coherent processors perfom stores simultaneously this results in cachelines being allocated in SMP which are not allocated when run in uniprocessor, resulting in a significant reduction in aggregate write bandwidth. for example, on Tegra 2 systems with 300MHz DDR main memory, running memset over a large buffer (i.e., L2 miss) on a single processor will achieve ~2GB/sec of write bandwidth, but if the same operation is run in parallel on both CPUs, the aggregate write bandwidth is just 500MB/sec changing the cache allocation policy to read-allocate reduces some of this performance loss on SMP systems. Change-Id: Ice47ab0a15f2490b7e9a007b4b37800566ed7be1 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08[ARM] tegra: remove inner-writeback memory type from SMP startupGary King
the memory remapping (NMRR) registers were configured differently by the SMP and LP2 startup code from the standard kernel. temporarily reverting the inner-writeback change for now. Change-Id: Ib9c4fc75580d1cc705a5dd83377c0703669bcabc Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08[ARM] mm: add page allocator for modifying cache attributesGary King
ARM CPUs with speculative prefetching have undefined behaviors when the same physical page is mapped to two different virtual addresses with conflicting cache attributes. since many recent systems include IOMMU functionality (i.e., remapping of discontiguous physical pages into a virtually-contiguous address range for I/O devices), it is desirable to support allocating any available OS memory for use by the I/O devices. however, since many systems do not support cache coherency between the CPU and DMA devices, these devices are left with using DMA-coherent allocations from the OS (which severely limits the benefit of an IOMMU) or performing cache maintenance (which can be a severe performance loss, particularly on systems with outer caches, compared to using DMA-coherent memory). this change adds an API for allocating pages from the OS with specific cache maintenance properties and ensures that the kernel's mapping of the page reflects the desired cache attributes, in line with the ARMv7 architectural requirements Change-Id: If0bd3cfe339b9a9b10fd6d45a748cd5e65931cf0 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08[ARM] mmu: add option to map lowmem with page mappingsGary King
add a kernel configuration to map the kernel's lowmem pages using PTE mappings, rather than the default behavior of 1MiB section mappings. on ARMv7 processors, to support allocating pages with DMA-coherent cache attributes, the cache attributes specified in the kernel's mapping must match cache attributes specified for other mappings; to ensure that this is the case, the kernel's attributes must be specified on a per-page basis. to avoid problems caused by the init_mm page table allocations exceeding the available initial memory, when this config is enabled lowmem is initially mapped using sections (matches current behavior), then remapped using pages after bootmem is initialized Change-Id: I8a6feba1d6806d007e17d9d4616525b0446c0fb1 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-08[ARM] tegra: i2s: Add I2S ioctl for setting bit formatChris Fries
Added an ioctl to set the bit format for I2S between "DSP"/"PCM" mode and normal mode (set by board file) Signed-off-by: Iliyan Malchev <malchev@google.com>
2010-10-07[ARM] tegra: irq: Implement retriggerColin Cross
Change-Id: I5be02f60f1b0f35835a8d05abdb2934cdafb1122 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-07[ARM] tegra: Combine tegra_fiq_select with enable/disableColin Cross
Change-Id: Iba3dc43e1a95993a6278eea008c7a8610ed0cd4c Signed-off-by: Colin Cross <ccross@android.com>
2010-10-06Revert "[ARM] tegra: driver for spdif audio"Iliyan Malchev
This reverts commit 3543d53703c5a1ed0b987c77e7a79226c3a24f45. Signed-off-by: Iliyan Malchev <malchev@google.com>
2010-10-06[ARM] tegra: i2s: Update pm_qos for 2.6.36Colin Cross
Change-Id: I205457db1432c672b026887defa8d498bc613412 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-06[ARM] tegra: correct device definition of second i2s controllerChris Fries
Signed-off-by: Iliyan Malchev <malchev@google.com>
2010-10-06[ARM] tegra: dma: fix a typoIliyan Malchev
Signed-off-by: Iliyan Malchev <malchev@google.com>
2010-10-06[ARM] tegra: driver for spdif audioRavindra Lokhande
-- creates /dev/spdif_out and /dev/spdif_out_ctl for playback and control settings. -- playback only Change-Id: I19af1d41e13dedef650784835339ef9718300d0c Signed-off-by: Iliyan Malchev <malchev@google.com>
2010-10-06[ARM] tegra: add spdif device and resourcesIliyan Malchev
Signed-off-by: Iliyan Malchev <malchev@google.com>
2010-10-06[ARM] tegra_i2s_audio: add more elaborate error countsIliyan Malchev
This patch replaces the error counter with two separate error counters, one for late dma callbacks, and another for overruns (during recording) or underruns (during playback). The ioctls TEGRA_AUDIO_IN_GET_ERROR_COUNT and TEGRA_AUDIO_OUT_GET_ERROR_COUNT now take a pointer to a struct containing both error counters. Signed-off-by: Iliyan Malchev <malchev@google.com>
2010-10-06[ARM] tegra_i2s_audio: use pm_qos to prevent DMA-callback delaysIliyan Malchev
Signed-off-by: Iliyan Malchev <malchev@google.com>
2010-10-06ARM: tegra: parent sclk on pll_m_out1 so it can run @ 240MhzDima Zavin
Since sclk no longer needs pll_p_out4, don't explicitly enable it. Change-Id: I47debdd3402e02967f77ebd4c3b8c4594ece4083 Signed-off-by: Dima Zavin <dima@android.com>
2010-10-06ARM: tegra: provide the correct max rates for pclk and sclkDima Zavin
Change-Id: Ieb1ae5356df26e0c9be631b9f58c641a350dc4eb Signed-off-by: Dima Zavin <dima@android.com>
2010-10-06ARM: tegra: add a virtual cop clock for AVP reset assertionDima Zavin
Change-Id: Ib27e5191d78f7994d444167b7d3a981a43f59b3c Signed-off-by: Dima Zavin <dima@android.com>
2010-10-06ARM: tegra: enable clk reset for non-peripheral clocksDima Zavin
Add a new 'reset' clk op. This can be provided for any clock, not just peripherals. Change-Id: I0742cfad1587ddc006066c7fa9bc22f180c04e6f Signed-off-by: Dima Zavin <dima@android.com>
2010-10-06tegrafb: add forward-decls for structs used in function prototypesGary King
Change-Id: Ief5f09f9340362197b01adeef28fbd42cd0a7a06 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-06tegra: iovmm-gart: move init call to subsys_initcallGary King
nvmap and nvhost will behave improperly if iovmm is not present when their respective devices are probed; however, the probe ordering depends on the order the initcalls are made to register the drivers. move iovmm-gart into subsys_initcall to ensure that it is registered earlier than other drivers Change-Id: If3e07ce239e593a0833a3381cd1132f5d6ef6786 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-06[ARM] tegra: ventana: fix pinmux for bluetooth and gas gaugeGary King
Fixes by Anantha Idapalapati <aidapalapati@nvidia.com> and Mayuresh Kulkarni <mkulkarni@nvidia.com> Change-Id: Ib7599d3593a8cc19b5b6dce451f3b203d4c5b70f Signed-off-by: Gary King <gking@nvidia.com>
2010-10-06[ARM] tegra: ventana: add OTG deviceGary King
Change-Id: Ie35453a385221b6d1f8b7eb05ed19e550a4c1d16 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-06[ARM] tegra: add tegra-otg and tegra_uart to devices.cGary King
Change-Id: Icdc0de036566220f337a21d5b1bae0e81057f115 Signed-off-by: Gary King <gking@nvidia.com>
2010-10-06[ARM] tegra: usb_phy: fix warningBenoit Goby
Change-Id: I10d3f7b001a13d4689adb64a7b4bf06626b6c786 Signed-off-by: Benoit Goby <benoit@android.com>
2010-10-06[ARM] tegra: ventana: register tps6586x interruptsGary King
configure the PMC interrupt polarity low, and register IRQ numbers with the TPS6586X core and RTC Change-Id: Iba08704bd1355ed00af3d9132118ce095c5118fe Signed-off-by: Gary King <gking@nvidia.com>
2010-10-06video: tegra: set output color depth on init/resumeErik Gilling
Signed-off-by: Erik Gilling <konkers@android.com> Change-Id: If7e0af98910c68cc53227990ab2970a934e3867c
2010-10-06[ARM] twd: Always calibrate local timerColin Cross
Change-Id: I075f883739d0eeea3b6b10da003119431cf3c2d2 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-06[ARM] twd: Fix updating control register in set_modeColin Cross
Change-Id: I5096cc3fedf51024c332adbb846689e01e1f7ce0 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-06enable tegra_i2s_audioIliyan Malchev
Change-Id: I0b6bfba1f2084d5d05929c2066a49a6c7413c54a Signed-off-by: Iliyan Malchev <malchev@google.com>
2010-10-06ARM: tegra: powergate the mpe and 3d cores at bootDima Zavin
Change-Id: I6ca09db039cd80eab18d062a7a4b5d2a93bd385e Signed-off-by: Dima Zavin <dima@android.com>
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