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2010-04-20tegra:disabling usb0 vbus as a wake sourcetegra-9.12.10Narendra Damahe
Bug 651676, this is causing failure while entering system suspend when lp0 is lowest power state Change-Id: I4337fc00571e21f9a6d39706b74ec62522cb6d46 Change-Id: I4337fc00571e21f9a6d39706b74ec62522cb6d46 Reviewed-on: http://git-master/r/1166 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-20tegra power: Enable CPU standby line during initialization.Venkata(Muni) Anda
CPU power request line needs to be explicitly enabled so that PMUs with separate request lines for CPU and core rails will shutdown the CPU power rail as expected. Change-Id: I95bc048b6e1df9029e900d33c4c0f5aa63c008a7 Reviewed-on: http://git-master/r/1156 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Venkata (Muni) Anda <vanda@nvidia.com>
2010-04-20tegra ODM: Added support for new E1108 board (rev B).Alex Frid
Change-Id: I50cb153fd240818ca876dda53a58809740a272d2 Reviewed-on: http://git-master/r/1141 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-20[ARM] tegra: fix errors in tegra pinmux tables for SPI, NAND, OWRRaj Mailapalli
Bug 671189, 663161 Tested on Nand + android. Change-Id: I518d8a1b57a9766dc69a115b1189789f054c2d0e Reviewed-on: http://git-master/r/1088 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-20tegra pm: adding a delay of 2ms after writing to APBDEV_PMC_CNTRL_0Mayuresh Kulkarni
It seems that after writing SYSCLK_OE bit in APBDEV_PMC_CNTRL_0, a delay needs to be added for stabilization. Reviewed by Bharat. Tested on Harmony (A02, R04 EC firmware) for multiple flash and reboot. Bug 676490 - [T20/Harmony] Bootup failure on harmony-inconsistent (3/5 times) Change-Id: I1f45a86aa23ac00b43f0103285cceda970ee5b39 Reviewed-on: http://git-master/r/1160 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-19tegra power: Spurious KBC interrupt WAR. Explicitly disable KBC interrupt.tkasivajhula
The interrupt flag in the 32KHz domain might not be getting cleared correctly. Clear the kbc interrupt explicitly prior to LP0 to fix this. Change-Id: I68c93cb3130fd123e28f1c697b9314b1bbcf4c6e Reviewed-on: http://git-master/r/1154 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
2010-04-19tegra nvmap: Enable CONFIG_DEVNVMAP_RECLAIM_UNPINNED_VMvdumpa
Bug 663285 Enable nvmap to reclaim unpinned I/O virtual memory after it has been unpinned and re-use it for other objects. Checking in on behalf of yhsu. Change-Id: I27304b45a80ae0d2fcad9f126672fe6ff5ded2af Reviewed-on: http://git-master/r/1144 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Tested-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-16tegra:low power state selection based on ODMDATA for whistler and HarmonyNarendra Damahe
Change-Id: I6969716342df0b28db1167df9bca50a5c03ffb2f Reviewed-on: http://git-master/r/1138 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-16tegra power: Flush the L2 rams before entering LP0.tkasivajhula
LP0 turns off core voltage. As a result, the L2 rams need to be flushed prior to shutdown. The L2 cache will be re-enabled after returning from LP0. Change-Id: Ie6e69a3e5615393c5c6e7189b4d7e3559304e7f9 Reviewed-on: http://git-master/r/1036 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-15tegra usb: Enabling busy hints for cpu clockAbhishek Aggarwal
To enhance the USB MSD performance, the busy hints for cpu clock have been enabled on cable connect and its frequency is being boosted to 300 MHz. Bug 654486: [whistler/android] - Large difference in USB MSD perf with DFS OFF Change-Id: I4471665bd02b7b49b368aec4aac5f1b89038c309 Reviewed-on: http://git-master/r/1114 Tested-by: Abhishek Aggarwal <aaggarwal@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-15tegra nvec: de-assert EC_REQUEST# properlyVarun Wadekar
Set the GPIO in a reasonable state before calling NvRmGpioConfigPins(Output) to avoid 5us~1ms low-pulse, since the low-pulse causes some EC firmwares to crash. reviewed by Artiste-Hsu tested on Harmony Change-Id: Ia30dfd10dfd16eec979f2a8e6ffc8286121a2eeb Reviewed-on: http://git-master/r/1126 Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Phillip Smith <psmith@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-15tegra:enable deep sleep as a lowest power mode for HarmonyNarendra Damahe
Change-Id: Ied68fde9cc9556088837ccaabfdd93c396777218 Reviewed-on: http://git-master/r/1130 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-15Enabled CONFIG_CGROUP_SCHED on WhistlerDavid Schalig
On Whistler enabled CONFIG_CGROUP_SCHED instead of CONFIG_USER_SCHED to be in sync with Harmony kernel config. Enables cgroup file system. Bug 669840 Change-Id: I4366b0ad0af5cb57fb7adc373347e081811d0590 Reviewed-on: http://git-master/r/1111 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-15tegra RM: Added PMU low power state configuration.Alex Frid
Added PMU low power state configuration to RM kernel suspend/resume. Included PMU interrupt control, and core rail control on platforms with combined cpu/core power request. Restricted core power groups gating to LP1 entry (core domain is down in LP0, anyway). Change-Id: If37ddfd42bd861b2cbc31767775583bd13549da8 Reviewed-on: http://git-master/r/1086 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-14tegra ODM: Updated EMC DVFS table on Whistler.Alex Frid
Updated EMC DVFS table on Whistler: - made sure RFC settings are above 5 for all entries - disabled DQS_PULLD for 150MHz entry and below - lowered operational voltage for 18MHz and 27MHz entries from 1.0V to 0.95V Change-Id: I682ed68bb5bfd4497a214065007159ab2fe042b7 Reviewed-on: http://git-master/r/1089 Reviewed-by: Sharad Ranjan <shranjan@nvidia.com> Tested-by: Sharad Ranjan <shranjan@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-14tegra RM: Disabled NOR clock.Alex Frid
Disabled NOR clock in RM ("orphan" boot clock). If/when NOR driver is added it will re-enable it as necessary. Change-Id: I5f9b15a5be86c594b6638c3110d9f1d8ba5db694 Reviewed-on: http://git-master/r/1116 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-13tegra uart: Fixing the tx and rx dma path issueLaxman Dewangan
Following issue has been fixed: - Blocking write was returning immediatly if data request is multiple of 4. - Blocking write was not able to complete if data length is nonmultiple of 4 and more than 4. - The close was taking too much time because proper timeout and fifo size was not configured. - Tx dma path optimized to fill more data to dma buffer if there is more pending chars in the buffer. - Tx path is fixed to properly signal the wakup event to tty layer. - RTS flow control is not getting set from second open even cflag is requested for that. - Rx dma was not receiving the correct data after second open. The multiple request was getting queued for the receive path at the time of closing. - Rx dma was started before uart controller is configured and it is creating to misbehave the dma. - Transfer count was not getting calculated in the dma driver. Pending issue: - Loosing the data id more than 32K of data was sennt is single shot. Debugging this. Tested on harmony with different testcase developed for testing the linux serial driver. Change-Id: I6ed9095dd6340d2b5e7ef036823d2e4e5a61abcc Reviewed-on: http://git-master/r/1065 Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Tested-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-13Fixing emc_log for AP20shranjan
patch: removing extra spaces Change-Id: Icc7fa7d5744134c0846b99c77b90cd76f9f938fc Reviewed-on: http://git-master/r/1068 Tested-by: Sharad Ranjan <shranjan@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-12tegra RM: Reduced LP2 entry threshold.Alex Frid
Adjusted LP2 time padding factor to reduce LP2 entry threshold back to 5ms (commit ad159fa937e9d917737956d12d530b723cba2b13 set it to 12.5ms as a side effect of adding power good delay to LP2 turnaround time) Change-Id: I1f00803e5d043cc6e99aeb7b373c0bdbda56e0ed Reviewed-on: http://git-master/r/1087 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-12[ARM] clean slave processor bootup page tables from L2Gary King
by the time that the slave processors' page table pointers are written to memory, the L1 and L2 caches may already be enabled on the master, so the writes need to be forcefully cleaned to memory to ensure that the slave will be able to read it. patch originally submitted to 2.6.34 by RMK Change-Id: Id9952149ce17c693775ec2b21e9a0425465fb770 Reviewed-on: http://git-master/r/1067 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-11tegra: invalidate CPU state when starting secondary processorScott Williams
tegra_secondary_startup was not invalidating the entire CPU state when bringing up a slave CPU. This change adds invalidation of the I-cache, TLB, and BTAC, and also enables the I-cache and branch prediction to speed up D-cache invalidation. Change-Id: I82b21dde7befb5ae634a72418b06892a30ec1ebf Reviewed-on: http://git-master/r/1069 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-09Adding the DSI display read response error codes.Nagesh Penumarty
Adding the following DSI read response error codes. DispDsiReadAckError, Acknowledge & Error read response. DispDsiReadInvalidResp, invalid read response. Bug 644992 Change-Id: Id629c05a0ce851a698d5028da138de942cedcc5c Reviewed-on: http://git-master/r/1059 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-09tegra RM: Reduced EMC activity margin.Alex Frid
Reduced EMC activity margin from 100% (2x) to 50% (1.5x) based on video use case experiments. Change-Id: I8467a52d00b62011516cefd040eb90f625f30d8d Reviewed-on: http://git-master/r/1062 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Niranjan Wartikar <nwartikar@nvidia.com> Tested-by: Niranjan Wartikar <nwartikar@nvidia.com> Reviewed-by: Sharad Ranjan <shranjan@nvidia.com> Tested-by: Sharad Ranjan <shranjan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-09tegra pmu: do not turn ON the LDO0 rail by defaultDeepesh Gujarathi
The LDO0 power rail was enabled during bootup by default, thereby increasing the ref count. This results in the rail remaining powered ON even when we try to disable it from a driver. Disabling the LDO0 by default, when there are no devices actively using it, should result in power saving. Change-Id: I19e478e9af2019de5e02ff9a31e7085e815ffaed Reviewed-on: http://git-master/r/1058 Reviewed-by: Kenneth A Radtke <kradtke@nvidia.com> Tested-by: Deepesh Subhash Gujarathi (Engrg-Mobile) <dgujarathi@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-08tegra RM: Updated tegra idle loop timing.Alex Frid
Updated tegra idle loop timing: - Added scheduler tick stop as a condition for LP2 entry; it made sure that jiffies are updated by the kernel after tegra idle code exit; hence, direct (unprotected) jiffies increment in idle code is removed - Rounded down sleep time estimate to avoid over-sleeping next interrupt in LP2 - Set more realistic LP2 turn-around time to take into account power rail transition time Change-Id: I7d97496b2f39d33a8150b51dfa152e72eb774fc0 Reviewed-on: http://git-master/r/1054 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-07tegra: fix pci root port 1 transactionsGary King
use inclusive addresses for the PCI memory aperture limits; otherwise, transactions destined for root port 1 show up on root port 0. originally reported by Ali Saidi (ali.saidi@arm.com) Change-Id: I48181325f6164159713139d4868cb12f6563f1ab Reviewed-on: http://git-master/r/1003 Reviewed-by: Jeremy Alves <jalves@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-07gpio: Configuring pinmux and power rail with gpio_request.Laxman Dewangan
When gpio client uses the direct linux api which is provided by gpio lib of linux kernel driver, the pinmux and io power rail was not getting configured. Configuring the pinux and power rail so that client can use direct gpio api of linux and need not to use the rm gpio wrapper api. Tested on whistler. Change-Id: I02b6782fd751543d064588288104a26caab7c848 Reviewed-on: http://git-master/r/1021 Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com> Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-07tegra: Fixed native timer event time calculationScott Williams
The native timer code to program the timer hardware for the next kernel event was incorrectly rescaling the cycle count which was passed in by the kernel. This would result in event periods 100000 times longer than expected. This error would occur only when LOCAL_TIMERS were not configured. Change-Id: I32a1593368510069afe1fb439465d6c9b696c4d3 Reviewed-on: http://git-master/r/1051 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-06tegra RM: Power gated core partitions on suspend entry.Alex Frid
Power gated all core partitions (except L2C) when entering suspend. During resume ungate those partitions that were powered before suspend. Change-Id: I6559f7d314df5904acc8f639efe953d8382925ac Reviewed-on: http://git-master/r/1046 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-05nvec_battery:Handling critical battery conditionSachin Nikam
1. nvec.h:Correcting enum ordering for NvEcBatterySubtype as per ECI specs. NvEcBatterySubtype_SetRemainingCapacityAlarm and NvEcBatterySubtype_GetRemainingCapacityAlar >> Verified 2. Registering interrupt for LOW_BAT# from T20 pinmux table:- GPIO interrupt for Low battery on port w and pin 3 >> Already verified on Wince. On Android when 0% power is left device is shutdown. Harmony has this setting around 9.3V which is less when the battery is at 0%. 3. Enabling LOW_BAT# as a wakeup source 11 from suspend >> As point no. 2 is wokring this should also work. This is not verfied as in suspend battery discharge is slow. 4. Enabling Low capacity alarm as a wakeup source suspend >> As remaining capacity alarm is working this should also work. This is not verfied as in suspend battery discharge is slow. 5. Setting the 10% of Design capacit as threshold for Remaining capacity alaram event. >> Verified 6. Adding 4 functions which are needed for EC firmware validation NvOdmBatterySetRemCapacityAlarm NvOdmBatteryGetRemCapacityAlarm NvOdmBatterySetConfiguration NvOdmBatteryGetConfiguration >> Verified 7. Calling kernel_power_off() when device is running on only battery and it is ctitically low to gracefully shutdown the system. >> Verified Tested on harmony + eclair + battery Change-Id: I6f4c8a1866ba63c293813b180cc5b74714aa23cd Reviewed-on: http://git-master/r/976 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-05tegra: Enabling Accelerometer Driver for whistler board.Vishwas Rao
This should enable accelerometer on Whistler. Change-Id: I884ef704083c8d5e1fe07554301eb28a2c24db49 Reviewed-on: http://git-master/r/987 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-02ARM/tegra: delete SDIO DDK and DDK-based MMC host drivertegra-9.12.9Gary King
Change-Id: I30872e9905b7bdf1cca56e53089e5cfde7586798 Reviewed-on: http://git-master/r/1026 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-01tegra mmc: enable MMC_UNSAFE_RESUME config for tegra_whistler_gnu_linuxDeepesh Gujarathi
Normally, when the system goes into suspend, all the storage cards are removed and later re-enumerated upon resume. During re-enumeration the device name and number are not guaranteed to be the same as they were during bootup. This can cause issues if rootfs falls on one such device. When the MMC_UNSAFE_RESUME config is enabled, it will prevent kernel from unmounting the mmc cards before suspend. Upon resume the cards will still be using the same device id as they were before suspend. Change-Id: Ibc1511c5feb0391dc644df2d710e386ec0d353ce Reviewed-on: http://git-master/r/994 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-01tegra RM: Updated VDE clock configuration policy.Alex Frid
Updated VDE clock configuration policy - allowed to use high frequency PLLC for VDE targets within 100MHz-200MHz range. This range was covered by low frequency PLLP0, but better divider granularity achieved with PLLC results in lower voltage requirements. Change-Id: I922dbd8db19dc19339db5bfbf2651604e28e789d Reviewed-on: http://git-master/r/1007 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Sharad Ranjan <shranjan@nvidia.com> Tested-by: Sharad Ranjan <shranjan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-01tegra pcie: add the VDD_1V5 power rail to the pcie guidDeepesh Gujarathi
As per the harmony power tree VDDIO_PEX_CLK is the T20's 3.3V PCIe supply. It is sourced from LDO0 of the PMU. By default, LDO0 is off. VDD_1V5 is the 1.5V supply for the PCI Express Mini Card connectors. It turns on automatically in tandem with the general-purpose 3.3V domain. If there are no active pcie devices on the bus turn off the VDD_1V5 power rail. Change-Id: I518368937aa36e7c73fbb93c28a39706903a614d Reviewed-on: http://git-master/r/1019 Reviewed-by: Kenneth A Radtke <kradtke@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-01tegra ODM: Changing pinmux configuration for UART-A when ULPI is used.Steve Lin
This fix corrects the pinmux configuration so UART-A is mapped to SDIO1 pins when ULPI is used. AP will be able to communicate with the ULPI modem through both UART and ULPI. Change-Id: I268a76496bd5371c2b757b0133eb0f276234504f Reviewed-on: http://git-master/r/1005 Tested-by: Szming Lin <stlin@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-01tegra usb: USB Host devices are not working on Whistlersgadagottu
With CL#5705540 USB host functionality on OTG port has broken on Whistler.Also Device dis-connection and connection on root port(USB3),makes host functionality broken. So this needs to debugged further. However for Harmony both USB1 device and USB3 integrated hub are working fine with-out any issue. So reverting the change for Whistler configuration only. Bug 669288 :[AP20/Android/Whistler]: USB devices not working. Tested on : Whistler and Harmony Tested for USB host functionality on OTG port Tested for USB host functionality on USB3 with multiple connection/dis-conenction. Change-Id: Id1c2157d796e095ff66e5002b5d00958a89a7bf7 Reviewed-on: http://git-master/r/1008 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Gary King <gking@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-01tegra: Fixed error module bond-out index calculationScott Williams
Fixed an incorrect calculation for skipping to the next byte of bond-out information. Bailing out of a byte early would result in an incorrect offset being used for subsequent module ids resulting in incorrect modules being marked as bonded out. Change-Id: Ia5cb449006c2d3b825097c852c21f4e1346e6696 Reviewed-on: http://git-master/r/1024 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-31ARM/tegra: add missing copyright attribution to cpuidle driverGary King
Change-Id: I1db2c4cba29e0d4c34cc7d34c4a1be0cfb13caa5 Reviewed-on: http://git-master/r/1002 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-31tegra RM: Moved AVP and EMC low corners.Alex Frid
Moved AVP low corner to 36MHz (from 24MHz) and EMC low corner for LPDDR2 platforms to 18MHz (from 50MHz), as determined by audio use case testing. Increased low corner detection hysteresis for CPU to 4MHz (from 1MHz), and removed half of activity margin from low corner hit requirements in case when no starvation/busy hints are present. Change-Id: Ia3ccbaefb542066a20a1ac238e88026655c76223 Reviewed-on: http://git-master/r/985 Reviewed-by: Niranjan Wartikar <nwartikar@nvidia.com> Tested-by: Niranjan Wartikar <nwartikar@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-31tegra: implement cpuidle device supportGary King
add LP2 (CPU power-gated) and LP3 (CPU flow-controlled) idle states for Tegra 2 CPUs through the kernel cpuidle interface exit latency for LP2 mode is a very rough approximation; the actual latency is dependend on the CPU frequency Change-Id: I115a3be6a065bcdad4149ce90cf4139b42062a43 Reviewed-on: http://git-master/r/951 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-30tegra mmc: enable MMC_UNSAFE_RESUME config for tegra_whistler_androidDeepesh Gujarathi
Normally, when the system goes into suspend, all the storage cards are removed and later re-enumerated upon resume. During re-enumeration the device name and number are not guaranteed to be the same as they were during bootup. This can cause issues if rootfs falls on one such device. When the MMC_UNSAFE_RESUME config is enabled, it will prevent kernel from unmounting the mmc cards before suspend. Upon resume the cards will still be using the same device id as they were before suspend. Change-Id: I2821b20bbd3ecb753bdc8c90297e41c396c66364 Reviewed-on: http://git-master/r/988 Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-30tegra pm: use blocking sysfs reads to notify nvrm_daemonKaz Fukuoka
bug 642072: Power Aware NvRM Daemon Use blocking sysfs reads to notify from pm_notifier (kernel) to nvrm_daemon (userspace). Change-Id: I9119733994613ac38c547ec7808c6afc811a25c2 Reviewed-on: http://git-master/r/984 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-30tegra-nvec: Report keystroke for the key that is used to wake up.Bharat Nihalani
With this change, display comes up with a single key press; but the catch is that it only works with "Windows" and "F3" keys. This limitation is posed by Android and not EC. NOTE that for other than "Windows" and "F3" key presses, the system does wake up, but an additional "Windows"/"F3" key press is still required to get the display up. Also, explicitly letting EC know that it should allow any keyboard/mouse event for wake-up. This is the default behavior, but still wanted to explicitly specify. Change-Id: I2a1e7d90fbbfd810f2334ee3832e193bfb5e45b1 Reviewed-on: http://git-master/r/986 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-29tegra odm: added IFF modem specific details to the odm kitSheshu Shenoy
Change-Id: Ie798a5dac7b450fd987f90d839549015c24ba2ce Reviewed-on: http://git-master/r/875 Tested-by: Sheshagiri Shenoy <sshenoy@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Michael Hsu <mhsu@nvidia.com> Tested-by: Michael Hsu <mhsu@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-29ARM: enable CONFIG_CPU_IDLE supportGary King
add ARCH_HAS_CPU_IDLE_WAIT and ARCH_HAS_DEFAULT_IDLE configuration, and expose default_idle and cpu_idle_wait cpu_idle_wait implementation based on the implementation in the x86 tree Change-Id: Ie24b6336db833cc638868abfdba822889646d0a8 Reviewed-on: http://git-master/r/950 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-29tegra RM: Updated graphics clock control.Alex Frid
Updated graphics clock control: added 2D/EPP frequency scaling following EMC clock, and reduced Host1x clock to 108 MHz to make sure it can be run at low voltage always (per previous evaluation Host1x at 83MHz works well with 240MHz cap on modules behind Host, hence 108MHz setting with current 300 MHz module cap). Change-Id: I9d5d89b38f08b99a805ad22459a84cb580dce05c Reviewed-on: http://git-master/r/981 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-29nvec_battery:registering battery as wakeup source and battery events.Sachin Nikam
1. Making Battery and AC present as a wakeup source 2. Registering battery events:present, charging, remaining capacity 3. Handling battery odm flags and events in nvec_battery.c Change-Id: I814960ab5f065e6aaad72ea1c403ad9c8d6a1af8 Reviewed-on: http://git-master/r/907 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-26tegra power: Clean up LP0 code and shuffle around scratch regs.tkasivajhula
The scratch registers had to be shuffled around a bit to match the bootrom's scratch map. Change-Id: Iddcefbd23fdaccb2215b70bc5f188fadaf8ec194 Reviewed-on: http://git-master/r/918 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-26tegra : Using the correct check to find out E1108 boardsgadagottu
Currenttly to check the board type E1108 in nvodm_query.c, function NvOdmIsE1108Hynix() is used. That is EMC DFS specific, so it is replaced with the generic check "NvOdmPeripheralGetBoardInfo(BOARD_ID_WHISTLER_E1108, &BoardInfo)". Bug 666427 : [whistler/android/power] - suspend power has increased by 4mW Tested on :Whistler E1108 Change-Id: I7c8cdb9da2891d3b8ade738509024a78f6f6d38b Reviewed-on: http://git-master/r/943 Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-01-28 20:48:20 +0000