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2011-05-11Merge branch 'gic-fasteoi' of git://linux-arm.org/linux-2.6-wd into devel-stableRussell King
2011-05-11ARM: GIC: Convert GIC library to use the IO relaxed operationsSantosh Shilimkar
The GIC register accesses today make use of readl()/writel() which prove to be very expensive when used along with mandatory barriers. This mandatory barriers also introduces an un-necessary and expensive l2x0_sync() operation. On Cortex-A9 MP cores, GIC IO accesses from CPU are direct and doesn't go through L2X0 write buffer. A DSB before writel_relaxed() in gic_raise_softirq() is added to be compliant with the Barrier Litmus document - the mailbox scenario. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com>
2011-05-11ARM: gic: use handle_fasteoi_irq for SPIsWill Deacon
Currently, the gic uses handle_level_irq for handling SPIs (Shared Peripheral Interrupts), requiring active interrupts to be masked at the distributor level during IRQ handling. On a virtualised system, only the CPU interfaces are virtualised in hardware. Accesses to the distributor must be trapped by the hypervisor, adding latency to the critical interrupt path in Linux. This patch modifies the GIC code to use handle_fasteoi_irq for handling interrupts, which only requires us to signal EOI to the CPU interface when handling is complete. Cascaded IRQ handling is also updated to use the chained IRQ enter/exit functions to honour the flow control of the parent chip. Note that commit 846afbd1 ("GIC: Dont disable INT in ack callback") broke cascading interrupts by forgetting to add IRQ masking. This is no longer an issue because the unmask call is now unnecessary. Tested on Versatile Express and Realview EB (1176 w/ cascaded GICs). Tested-and-reviewed-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Tested-and-acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-05-11ARM: tegra: irq: Add tegra_eoiColin Cross
Implement irq_eoi to allow the GIC irq chip flow controller to be changed to fasteoi. Signed-off-by: Colin Cross <ccross@android.com>
2011-05-11ARM: tegra: irq: Move legacy_irq.c into irq.cColin Cross
Now that irq.c is just an interface layer between the gic and legacy_irq.c, move the contents of legacy_irq.c into irq.c. Signed-off-by: Colin Cross <ccross@android.com>
2011-05-11ARM: tegra: irq: Remove PM supportColin Cross
Tegra PM irq support is being improved, remove it for now until the rest of the platform gets PM support. Signed-off-by: Colin Cross <ccross@android.com>
2011-05-11ARM: tegra: irq: convert to gic arch extensionsColin Cross
Replace the ugly hack that inserts legacy irq controller calls into the irq call paths by reading and replacing the gic irq chip with the new gic arch extensions. Signed-off-by: Colin Cross <ccross@android.com>
2011-05-11ARM: tegra: update GPIO chained IRQ handler to use entry/exit functionsWill Deacon
This patch updates the Tegra gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. This is required for the GIC to move to fasteoi interrupt handling. Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-05-11ARM: nmk: update GPIO chained IRQ handler to entry/exit functionsWill Deacon
This patch updates the Nomadik gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. Cc: Rabin Vincent <rabin@rab.in> Cc: Grant Likely <grant.likely@secretlab.ca> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-05-11ARM: msm: update GPIO chained IRQ handler to use entry/exit functionsWill Deacon
This patch updates the MSM gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. Tested-and-reviewed-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-05-11ARM: s5pv310: update IRQ combiner to use chained entry/exit functionsWill Deacon
This patch updates the IRQ combiner chained IRQ handler code to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. This is required for the GIC to move to fasteoi interrupt handling. Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-05-11ARM: omap: update GPIO chained IRQ handler to use entry/exit functionsWill Deacon
This patch updates the OMAP gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. Cc: Colin Cross <ccross@google.com> Cc: Tony Lindgren <tony@atomide.com> Tested-and-acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-05-07Merge branch 'zImage_fixes' of git://git.linaro.org/people/nico/linux into ↵Russell King
devel-stable
2011-05-07ARM: zImage: make sure no GOTOFF relocs are used with .bss symbolsNicolas Pitre
To be able to relocate the .bss section at run time independently from the rest of the code, we must make sure that no GOTOFF relocations are used with .bss symbols. This usually means that no global variables can be marked static unless they're also const. To enforce this, suffice to fail the build whenever a private symbol is allocated to .bss and list those symbols for convenience. The user_stack and user_stack_end labels in head.S were converted into non exported symbols to remove false positives. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
2011-05-07ARM: zImage: remove the static qualifier from global data variablesNicolas Pitre
To be able to relocate the .bss section at run time independently from the rest of the code, we must make sure that no GOTOFF relocations are used with .bss symbols. This usually means that no global variables can be marked static unless they're also const. Let's remove the static qualifier from current offenders, or turn them into const variables when possible. Next commit will ensure the build fails if one of those is reintroduced due to otherwise enforced coding standards for the kernel. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
2011-05-07ARM: zImage: don't ignore error returned from decompress()Nicolas Pitre
If decompress() returns an error without calling error(), we must not attempt to boot the resulting kernel. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
2011-05-07ARM: zImage: simplify decompress_kernel()Nicolas Pitre
The return value for decompress_kernel() is no longer used. Furthermore, this was obtained and stored in a variable called output_ptr which is a complete misnomer for what is actually the size of the decompressed kernel image. Let's get rid of it. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
2011-05-07ARM: zImage: no need to get the decompressed size from the filesystemNicolas Pitre
In commit d239b1dc093d the hardcoded 4x estimate for the decompressed kernel size was replaced by the exact Image file size and passed to the linker as a symbol value. Turns out that this is unneeded as the size is already included at the end of the compressed piggy data. For those compressed formats that don't include this data, the build system already takes care of appending it using size_append in scripts/Makefile.lib. So let's use that instead. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
2011-05-07ARM: zImage: the page table memory must be considered before relocationNicolas Pitre
For correctness, the initial page table located right before the decompressed kernel should be considered when determining if relocation is required. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com>
2011-05-07ARM: zImage: make sure not to relocate on top of the relocation codeNicolas Pitre
If the zImage load address is slightly below the relocation address, there is a risk for the copied data to overwrite the copy loop or cache flush code that the relocation process requires. Always bump the relocation address by the size of that code to avoid this issue. Noticed by Tony Lindgren <tony@atomide.com>. While at it, let's start the copy from the restart symbol which makes the above code size computation possible by the assembler directly (same sections), given that we don't need to preserve the code before that point anyway. And therefore we don't need to carry the _start pointer in r5 anymore. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
2011-05-06ARM: zImage: Fix bad SP address after relocating kernelTony Lindgren
Otherwise cache_clean_flush can overwrite some of the relocated area depending on where the kernel image gets loaded. This fixes booting on n900 after commit 6d7d0ae51574943bf571d269da3243257a2d15db (ARM: 6750/1: improvements to compressed/head.S). Thanks to Aaro Koskinen <aaro.koskinen@nokia.com> for debugging the address of the relocated area that gets corrupted, and to Nicolas Pitre <nicolas.pitre@linaro.org> for the other uncompress related fixes. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-05-06ARM: zImage: make sure the stack is 64-bit alignedNicolas Pitre
With ARMv5+ and EABI, the compiler expects a 64-bit aligned stack so instructions like STRD and LDRD can be used. Without this, mysterious boot failures were seen semi randomly with the LZMA decompressor. While at it, let's align .bss as well. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> CC: stable@kernel.org
2011-05-06Merge branch 'master' of ↵Ingo Molnar
ssh://master.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into perf/urgent
2011-05-05Merge branch 'for-linus' of git://github.com/at91linux/linux-2.6-at91Linus Torvalds
* 'for-linus' of git://github.com/at91linux/linux-2.6-at91: at91: Add ARCH_ID and basic cpu macros definition for 5series chips family. arm: at91: fix compiler warning for eb01 board build arm: at91: minimal defconfig for at91x40 SoC ARM: at91: AT91CAP9 has a macb device
2011-05-04Merge branch 'perf/urgent' of ↵Ingo Molnar
git://git.kernel.org/pub/scm/linux/kernel/git/frederic/random-tracing into perf/urgent
2011-05-03Merge git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into devel-stableRussell King
2011-05-03ARM: PJ4: remove the ARMv6 compatible cache method entriesNicolas Pitre
The Marvell PJ4 is ARMv7 capable, so we don't support it in ARMv6 mode anymore. Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Acked-by: Saeed Bishara <saeed.bishara@gmail.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2011-05-03ARM: Sync Marvell Dove defconfig with latest kernelKonstantin Porotchkin
Re-generate defconfig for Marvell Dove platform Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
2011-05-03ARM: Moving Marvell Dove platform defaults to ARMv7Konstantin Porotchkin
Disabled legacy support for ARMv6 architecture on Dove platform. Latest Dove HW uses only ARMv7 model. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
2011-05-02Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm: (47 commits) CLKDEV: Fix clkdev return value for NULL clk case ARM: 6891/1: prevent heap corruption in OABI semtimedop ARM: kprobes: Tidy-up kprobes-decode.c ARM: kprobes: Add emulation of hint instructions like NOP and WFI ARM: kprobes: Add emulation of SBFX, UBFX, BFI and BFC instructions ARM: kprobes: Add emulation of MOVW and MOVT instructions ARM: kprobes: Reject probing of undefined data processing instructions ARM: kprobes: Remove redundant code in space_1111 ARM: kprobes: Fix emulation of PLD instructions ARM: kprobes: Reject probing of SETEND instructions ARM: kprobes: Consolidate stub decoding functions ARM: kprobes: Reject probing of all coprocessor instructions ARM: kprobes: Fix emulation of USAD8 instructions ARM: kprobes: Fix emulation of SMUAD, SMUSD and SMMUL instructions ARM: kprobes: Fix emulation of SXTB16, SXTB, SXTH, UXTB16, UXTB and UXTH instructions ARM: kprobes: Reject probing of undefined media instructions ARM: kprobes: Add emulation of RBIT instruction ARM: kprobes: Reject probing of LDRB instructions which load PC ARM: kprobes: Fix emulation of LDRD and STRD instructions ARM: kprobes: Reject probing of LDR/STR instructions which update PC unpredictably ...
2011-04-29Merge branch 'omap-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: OMAP3+: voltage: remove initial voltage OMAP4: Intialize IVA Device in addition to DSP device. omap: rx51: mark reserved memory earlier OMAP3: l3: fix for "irq 10: nobody cared" message arm: omap2: enable smc instruction for sleep34xx OMAP2/3: hwmod: fix gpio-reset timeouts seen during bootup. OMAP3: PM: Do not rely on ROM code to restore CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL OMAP2+: PM: Fix the saving of CM_AUTOIDLE_PLL register on scratchpad area OMAP4: clock data: Change DSS clock aliases OMAP2+: hwmod data: Fix wrong dma_system end address
2011-04-29ARM: 6891/1: prevent heap corruption in OABI semtimedopDan Rosenberg
When CONFIG_OABI_COMPAT is set, the wrapper for semtimedop does not bound the nsops argument. A sufficiently large value will cause an integer overflow in allocation size, followed by copying too much data into the allocated buffer. Fix this by restricting nsops to SEMOPM. Untested. Cc: stable@kernel.org Signed-off-by: Dan Rosenberg <drosenberg@vsecurity.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-04-29Merge branch 'kprobes' of git://git.linaro.org/people/nico/linux into fixesRussell King
2011-04-28ARM: kprobes: Tidy-up kprobes-decode.cJon Medhurst
- Remove coding standard violations reported by checkpatch.pl - Delete comment about handling of conditional branches which is no longer true. - Delete comment at end of file which lists all ARM instructions. This duplicates data available in the ARM ARM and seems like an unnecessary maintenance burden to keep this up to date and accurate. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Add emulation of hint instructions like NOP and WFIJon Medhurst
Being able to probe NOP instructions is useful for hard-coding probeable locations and is used by the kprobes test code. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Add emulation of SBFX, UBFX, BFI and BFC instructionsJon Medhurst
These bit field manipulation instructions occur several thousand times in an ARMv7 kernel. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Add emulation of MOVW and MOVT instructionsJon Medhurst
The MOVW and MOVT instructions account for approximately 7% of all instructions in a ARMv7 kernel as GCC uses them instead of a literal pool. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Reject probing of undefined data processing instructionsJon Medhurst
The instruction decoding in space_cccc_000x needs to reject probing of instructions with undefined patterns as they may in future become defined and then emulated faultily - as has already happened with the SMC instruction. This fix is achieved by testing for the instruction patterns we want to probe and making the the default fall-through paths reject probes. This also allows us to remove some explicit tests for instructions that we wish to reject, as that is now the default action. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Remove redundant code in space_1111Jon Medhurst
The tests to explicitly reject probing CPS, RFE and SRS instructions are redundant as the default case is now to reject undecoded patterns. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Fix emulation of PLD instructionsJon Medhurst
The PLD instructions wasn't being decoded correctly and the emulation code wasn't adjusting PC correctly. As the PLD instruction is only a performance hint we emulate it as a simple nop, and we can broaden the instruction decoding to take into account newer PLI and PLDW instructions. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Reject probing of SETEND instructionsJon Medhurst
The emulation of SETEND was broken as it changed the endianess for the running kprobes handling code. Rather than adding a new simulation routine to fix this we'll just reject probing of SETEND as these should be very rare in the kernel. Note, the function emulate_none is now unused but it is left in the source code as future patches will use it. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Consolidate stub decoding functionsJon Medhurst
Following the change to remove support for coprocessor instructions we are left with three stub functions which can be consolidated. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Reject probing of all coprocessor instructionsJon Medhurst
The kernel doesn't currently support VFP or Neon code, and probing of code with CP15 operations is fraught with bad consequences. Therefore we don't need the ability to probe coprocessor instructions and the code to support this can be removed. The removed code also had at least two bugs: - MRC into R15 should set CPSR not trash PC - LDC and STC which use PC as base register needed the address offset by 8 Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Fix emulation of USAD8 instructionsJon Medhurst
The USAD8 instruction wasn't being explicitly decoded leading to the incorrect emulation routine being called. It can be correctly decoded in the same way as the signed multiply instructions so we move the decoding there. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Fix emulation of SMUAD, SMUSD and SMMUL instructionsJon Medhurst
The signed multiply instructions were being decoded incorrectly. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Fix emulation of SXTB16, SXTB, SXTH, UXTB16, UXTB and UXTH ↵Jon Medhurst
instructions These sign extension instructions are encoded as extend-and-add instructions where the register to add is specified as r15. The decoding routines weren't checking for this and were using the incorrect emulation code, giving incorrect results. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Reject probing of undefined media instructionsJon Medhurst
The instructions space for media instructions contains some undefined patterns. We need to reject probing of these because they may in future become defined and the kprobes code may then emulate them faultily. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Add emulation of RBIT instructionJon Medhurst
The v6T2 RBIT instruction was accidentally being emulated correctly, this patch adds correct decoding for the instruction. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Reject probing of LDRB instructions which load PCJon Medhurst
These instructions are specified as UNPREDICTABLE. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-04-28ARM: kprobes: Fix emulation of LDRD and STRD instructionsJon Medhurst
The decoding of these instructions got the register indexed and immediate indexed forms the wrong way around, causing incorrect emulation. Instructions like "LDRD Rx, [Rx]" were corrupting Rx because the base register writeback was being performed unconditionally, overwriting the value just loaded from memory. The fix is to only writeback the base register when that form of the instruction is used. Note, now that we reject probing writeback with PC the emulation code doesn't need the check rn!=15. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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