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2012-08-29i.MX6: mx6q_sabrelite: set MTD size for SPI Nor to match U-BootEric Nelson
2012-08-29wl12xx_sdio: reset during op_remove_interfaceEric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-07-03Merge branch 'boundary-L3.0.15_12.04.01' of ↵3.0-boundary-imx6-201207031704Troy Kisky
github.com:boundarydevices/linux-imx6 into boundary-L3.0.15_12.04.01
2012-07-03sabrelite: allow gigabit, 0 tx delay, set phy irqTroy Kisky
2012-06-29nitrogen6x_defconfig: configure egalax_ts for single-touchEric Nelson
2012-06-27nitrogen6x_defconfig: add support for Focaltech ft5x06 multi-touch driverEric Nelson
2012-06-27i.MX6: mx6q_sabrelite: Add support for FocalTech ft5x06 driverEric Nelson
2012-06-26i.MX6: mx6q_sabrelite: swap SD cards to have numbering match U-BootEric Nelson
2012-06-26i.MX6: nitrogen6x: configure SD1 clock as 32K oscillator for TWL12xx slow clockEric Nelson
2012-06-25i.MX6: nitrogen6x_defconfig: add AUTOFS4 in kernelEric Nelson
2012-06-25i.MX6: nitrogen6x: set SD2 pads for SDIO if WiFi is enabledEric Nelson
2012-06-24i.MX6: Nitrogen6X: Add nitrogen6x_defconfig (no TWL12XX support yet)Eric Nelson
2012-06-24i.MX6: mx6q_sabrelite: add WL1271 support on SDHC2Eric Nelson
2012-06-24mmc: esdhc: add caps flag to esdhc_platform_dataTroy Kisky
2012-06-24i.MX6: mx6q_sabrelite: rework usdhc pad setup to be table-drivenEric Nelson
2012-06-24i.MX6Q: mx6q_sabrelite: Add TSC2004 touch screen supportEric Nelson
2012-06-24mx6qsabrelite: move HDMI to IPU0/DI1 to separate it from the parallel RGB ↵Eric Nelson
display
2012-06-24Sabrelite: IMX_HAVE_PLATFORM_IMX_DVFS, IMX_HAVE_PLATFORM_IMX_MIPI_CSI2Troy Kisky
2012-06-24i.MX6: mx6q_sabrelite: Sabre Lite doesn't expose UART3, Nitrogen6W doesEric Nelson
2012-06-24i.MX6: mx6q_sabrelite: set up UART3 (/dev/ttymxc2) with RTS, CTS on pins ↵Eric Nelson
EIM_D23-25,EIM_D31
2012-06-24i.MX6Q: mx6q_sabrelite: Add PWM0 backlight (on DRGB connector)Eric Nelson
2012-06-24i.MX6Q: mx6q_sabrelite: fix SDHC write-protect pinsEric Nelson
SDHC4 is microSD and has no write-protect pin on Sabre Lite or Nitrogen6X SDHC3 is microSD on Nitrogen6X, full-size SD on Sabre Lite
2012-06-24i.MX6: mx6q_sabrelite: route SGTL5000 to audmux 3 on Nitrogen6Eric Nelson
2012-06-24i.MX6: mx6q_sabrelite: Add Nitrogen6W detectionEric Nelson
2012-06-24fix execute permissionsTroy Kisky
2012-04-28ENGR00181191 MX6: set ipu2_clk parent from pll2_pfd_400MWayne Zou
On mx6dl, set ipu2_clk's parent from pll2_pfd_400M. On mx6q, ipu2_clk's parent from mmdc_ch0_axi_clk, and it is 264MHz by default. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-28ENGR00181107 add dma_alloc_writethrough functionSandor Yu
add dma_alloc_writethrough function to dma_mapping.c Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-04-27ENGR00180424: Changed iomux ID pinGuillermo
Changed iomux MX6Q ID pin to MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID Signed-off-by: Guillermo <b12356@freescale.com>
2012-04-27ENGR00180076: prompt "mmc0: error -110 during resume" with atheros wifi cardjustin.jiang
* only happend on sabre-auto board,atheros sdio wifi card can't be used after suspend/resume * Fix by keeping sdio power at suspend. Signed-off-by: justin.jiang <b31011@freescale.com>
2012-04-26ENGR00180882- MX6DL Add bus frequency scaling support.Ranjani Vaidyanathan
Added support for changing DDR frequency on MX6DL. During system IDLE, DDR freq can drop down to 24MHz if none of the devices that need high AHB frequency are active. Changed the DDR code to handle both MX6Q and MX6DL DDR and IOMUX settings. Fixed bug associated incorrect IRAM memory allocation used to store DDR and IOMUX data. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-26ENGR00180185: MX6-Add support for low power audio playbackRanjani Vaidyanathan
The DDR frequency needs to be at 50MHz for low power audio playback. So added a new low power mode for audio. Set the AHB to 25MHz, AXI to 50MHz and DDR to 50MHz in this mode. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-20ENGR00180412 MX6 SATA: Enable PHY in the SATA initilizationRichard Zhu
iENGR00179574: MX6- Add bus frequency scaling support disable SATA PHY defaultly Enable PHY in the SATA initilization, make sure the SATA work well. Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-04-19ENGR00180230 MX6 PCIE: enlarge the eye diagram and force to GEN1Richard Zhu
* Adjust the parameters, enlarge the eye diagram. * Force to the PCIE GEN1 speed. Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-04-19ENGR00180096 change NAND clock source to pll2_pfd_400MAllen Xu
change clock source explicitly by calling set_parent() function Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-17ENGR00179804 change NAND clock source from pll2_pfd_352M to pll2_pfd_400MAllen Xu
Due to pll2_pfd_352M would be used for LVDS, change NAND clock source to pll2_pfd_400M. Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-17ENGR00179685 MX6 clock:Cleanup LDB DI parent clockLiu Ying
According to ticket TKT071080, 0b011 for ldb_dix_clk_sel field in CCM_CS2CDR is changed from pll3_pfd_540M to mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1. However, MX6DL uses mmdc_ch1 as LDB DI parent clock. This patch corrects the LDB DI parent clock setting. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-04-16ENGR00179747: MX6DL-Fix boot failureRanjani Vaidyanathan
Fix the boot failure caused by: 8f0c21e06d4f7d0c7c078d6261ccd75f2a45c3ab MX6- Add bus frequency scaling support There is no SATA on MX6DL. Accessing SATA PHYs early in the boot process causes the system to crash. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-16ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1Liu Ying
This patch corrects LDB DI clock's parent clock to be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0 according to ticket TKT071080(0b011 for ldb_dix_clk_sel field in CCM_CS2CDR is changed from pll3_pfd_540M to mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1). Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-04-13ENGR00179574: MX6- Add bus frequency scaling supportRanjani Vaidyanathan
Add support for scaling the bus frequency (both DDR and ahb_clk). The DDR and AHB_CLK are dropped to 24MHz when all devices that need high AHB frequency are disabled and the CORE frequency is at the lowest setpoint. The DDR is dropped to 400MHz for the video playback usecase. In this mode the GPU, FEC, SATA etc are disabled. To scale the bus frequency, its necessary that all cores except the core that is executing the DDR frequency change are in WFE. This is achieved by generating interrupts on un-used interrupts (Int no 139, 144, 145 and 146). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-13ENGR00179582 MX6: Bypass PLL1 during WAITRanjani Vaidyanathan
When system is going to enter WAIT mode, set PLL1 to 24MHz so that ARM is running at 24MHz. This is a SW workaround for the WAIT mode issue. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-13ENGR00179631 MX6 SabreSD: Add MIPI DSI Display supportWayne Zou
Add MIPI DSI Display support on mx6 SabreSD board. MIPI DSI needs pll3_pfd_540M clock source for 540MHz. if using ldb, the pll3_pfd_540M clock will be changed to 454Mhz. So add command line option disable_ldb when using MIPI DSI display. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-13ENGR00179628-2 MX6: add ssi info in sdmaGary Zhang
add ssi dual-fifo info in sdma structure Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-04-13ENGR00179621 MX6 PCIE: bring up PCIE on i.MX6 SD boardRichard Zhu
* Bring up the PCIE on i.MX6 SD board * Add the PCIE PHY access routines * Wrapper the board related codes by register one platform driver and data Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-04-13ENGR00179498-2 SDMA: fix p2p sdma script errorChen Liangjun
Update p2p script firmware address in plat-imx-dma.c for MX6Q. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-04-12ENGR00179284-2 support ONFI NAND device on mx6q_arm2_pop boardAllen Xu
enable ONFI NAND feature by command line parameter "onfi_support" Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-12ENGR00179497-2 MX6Q SabreSD: fix SPI nor flash pin configRobin Gong
Default SPI nor flash pin config is wrong, correct it for SabreSD RevB Signed-off-by: Robin Gong <B38343@freescale.com>
2012-04-11ENGR00177241-1 mx6 close APBH DMA clock when no I/O operationAllen Xu
When there is no NAND I/O operation, close all the reference clock, include GPMI,BCH and APBH clock. Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-10ENGR00179129 Board support for I2C AMFM module for IMX6Q and IMX6DLAlejandro Sierra
Modifications in ARD board file to support the Audio for AMFM module for IMX6Q and IMX6DL (REV A and REV B) Supported for kernel 3.0.15. Also it contains the I2C configuration for the AMFM module. Signed-off-by: Alejandro Sierra <b18039@freescale.com>
2012-04-09ENGR00179135: workaroud for hung in flush_cache_user_range()Huang Shijie
This patch is from Russell King's email. It's just a workaroud for a known but not fixed issue, please read the following email: http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/073083.html The root cause of this bug is : "We cant be holding the mmap_sem while calling flush_cache_user_range because the flush can fault. If we fault on a user address, the page fault handler will try to take mmap_sem again. Since both places acquire the read lock, most of the time it succeeds. However, if another thread tries to acquire the write lock on the mmap_sem (e.g. mmap) in between the call to flush_cache_user_range and the fault, the down_read in do_page_fault will deadlock." Please read the email: http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/071708.html It seems from arm-v6, the cache flush can cause a page fault. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-04-06ENGR00178875-1 VDOA: Add vdoa support on i.MX6 SOC platformWayne Zou
Add vdoa support on i.MX6 SOC platform Signed-off-by: Wayne Zou <b36644@freescale.com>
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