Age | Commit message (Collapse) | Author |
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The size was incorrect for the DmaVirtAddr, and SrcVirtAddr and
DestVirtAddr were incremented inside the loop, hence were not
the original ones that got mapped.
Also fix two ASSERTs.
Bug 698416
Change-Id: Ia53618f1fe9b3dd45de8194e0d082333c1d9573c
Reviewed-on: http://git-master/r/2833
Reviewed-by: David Le Tacon <dletacon@nvidia.com>
Tested-by: David Le Tacon <dletacon@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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copy the ODM query SDIO property for removable hosts into the
new platform data is_removable field
Change-Id: I29d2c9b6691707438711f0691d8392b3ab87824c
Reviewed-on: http://git-master/r/2889
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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hosts with non-removable cards should not need to specify
MMC_CAP_POLLING; this causes additional exits from the CPU idle
loop.
add a field to the platform data to specify that the host is
removable, and initialize card_present to true if the host
is not removable
Change-Id: I55d9c8295435deb522977b3e7380abc0f8f05721
Reviewed-on: http://git-master/r/2888
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Adding apis for following function to hooking up tegra serial driver with
bluesleep power management:
- Clock off.
- Clock on.
- Setting flow control to desired state.
- Checking for tx fifo status.
Following 4 state of uart state machine is developed to achieve this:
UART_CLOSED, UART_OPENED, UART_SUSPEND, UART_CLOCK_OFF.
The transitions of states are as follows:
UART_CLOSED: the init state on which resource is allocated but not
opened by client or when device is closed.
UART_OPENED: Able to do data transfer.
CLOSED to OPENED by opening the port.
CLOCK_OFF to OPENED by calling function tegra_uart_request_clock_on().
SUSPEND to OPENED by calling resume().
UART_CLOCK_OFF: The controller clock is disabled and so no data transfer
can happen. At this state, controller is not ready for
deep power down.
OPENED to CLOCK_OFF by calling tegra_uart_request_clock_off().
Can not go to this state from CLOSED and SUSPEND.
UART_SUSPEND: The controller is in suspended state and ready for deep power down.
UART_CLOCK_OFF to SUSPEND:
OPENED to SUSPEND.
Change-Id: Ib0c40547665181cadd172840be9aed2cc18ba448
Reviewed-on: http://git-master/r/2819
Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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fix a typo in the timer init code where max_delta_ns was being filled
in twice, rather than min_delta_ns.
Change-Id: I0efbadae265f408ec755658ddfa707fbd9906c75
Reviewed-on: http://git-master/r/2895
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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(A) Interval (... 90C) - no throttling, free running system
(B) Interval (90C, 115C) - active throttling of CPU frequency with
- gradient: -100 MHz/2 sec
- low limit: 50% of CPU frequency maximum
(C) Above 115C - h/w shutdown.
Bug 528708
Change-Id: Id4d57521f378eb72e740c9dc55a2814f8100384e
Reviewed-on: http://git-master/r/2851
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Change-Id: Id776c15b3f4810e7051e830d6b7dace71c6ee7cd
Reviewed-on: http://git-master/r/2779
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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bug 700135
Change-Id: I8f81011285f62e09b05449e6c3247eca4b306898
Reviewed-on: http://git-master/r/2879
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Bug 700052
Change-Id: If09da670f424b45a94ee609c2288adb7c6d69272
Reviewed-on: http://git-master/r/2839
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Change-Id: I2a6f3cf153ea7769c282cc556859a9ac66cabb38
Reviewed-on: http://git-master.nvidia.com/r/2829
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Fix undefined/unused references when CONFIG_PM is disabled.
Change-Id: I503cec11987b63e5750a05d0e7acc3238cdb363b
Reviewed-on: http://git-master.nvidia.com/r/2799
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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detecting USB VBUS through the PMU on supported platforms can save power
by turning off USB when there is no cable connection
Change-Id: I7c7782360c022aaec9708b8e3abc54d995639756
Reviewed-on: http://git-master/r/2801
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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With the MMU on, the instruction prefetcher
can potentially fetch instructions from memory
as the CPU is losing power. This can cause SDRAM to hang.
Change-Id: Iee4a40cc65f25a5969c443710c3a446befd07f41
Reviewed-on: http://git-master/r/2789
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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It is observed that the dma interrupt has the lower priority then
its client interupt priority. When client's isr calls dma get transfer,
the dma status has not been upated as dma isr have not been served yet.
So before reading the status, explicitly checking the interrupt status and
handling accordingly.
The another issue which is observed is that if dma has transferred the data
of amount = requested -4 and if it moves to invalid requestor before stopping
then status got reset and tarnsfered bytes becomes 0. This seems the apb dma
hw behavior. Following is the suggestion to overcome this issue:
- Disable global enable bit.
- Read status.
- Stop dma.
- Enable global status bit.
Added this workaround and it worked fine.
Change-Id: I5d12d2b655cc21d47b906de70165e8034a9233df
Reviewed-on: http://git-master/r/2580
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Enable kernel filter / nat tables for iptables program. Enable
Android USB RNDIS gadget.
Change-Id: I684771da7bcf260b2f9dd6c02b0100fdcc7191a4
Reviewed-on: http://git-master/r/2604
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Tested-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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In order to USB camera to work needs Video for Linux
framework and USB Video Class support.
Enabling CONFIG variables for V4L2 and UVC.
Change-Id: I8c9a0c9082a0be2f86621348edeb0a89a26375f6
Reviewed-on: http://git-master/r/2742
Tested-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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McErrorIntHandler() is no longer used. Remove it.
Change-Id: Ie63c2227bd9090fa2873ac17fadf2ed2fc3f4395
Reviewed-on: http://git-master/r/2795
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Add rndis USB function and platform device to tegra board
config.
Bug 693505
Change-Id: I4e8a16948f4081e7387502bed8f02991d9b4bd7c
Reviewed-on: http://git-master/r/2600
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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not all continuous clients will need callbacks for halfbuffer full, so
handle NULL callback functions as no-ops.
also, since CH_MIN is used as the channel for shared DMA interrupts, it
needs to be reserved so that it isn't allocated for exclusive clients
Change-Id: I7880eaeb0e7151b7617f7f93e83029797d2ad0f4
Reviewed-on: http://git-master/r/2733
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Setting the sdio pad strength to optimal value('0xC')
Bug ID: 687140
Change-Id: I1ddf930f7030baa60dba0267a4cc93b35beb3689
Reviewed-on: http://git-master/r/2738
Tested-by: Kapil Hali <khali@nvidia.com>
Reviewed-by: Rahul Bansal <rbansal@nvidia.com>
Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
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Change-Id: I0841c494462e4c2b2fd9f58cc0a3ad0305e5914a
Reviewed-on: http://git-master/r/2735
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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This avoids races in the VFP code where the dead thread may have
state on another CPU. By moving this code to exit_thread(), we
will be running as the thread, and therefore be running on the
current CPU.
This means that we can ensure that the only local state is accessed
in the thread notifiers.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Change-Id: I195ea8ce8f5f438166b402411eaff3f33f4b2490
Reviewed-on: http://git-master/r/2731
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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When the VFP notifier is called for flush_thread(), we may be
preemptible, meaning we might migrate to another CPU, which means
referencing the current CPU number without some form of locking is
invalid, and can cause data corruption.
For the most cases, this isn't a problem since atomic notifiers are run
under rcu lock, which for most configurations results in preemption
being disabled - except when the preemptable tree-based rcu
implementation is selected.
Let's make it safe anyway.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Change-Id: Ib6b75f8fc31efac2a874494af576fc334e2771d4
Reviewed-on: http://git-master/r/2730
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Bug 596345
Fixes USB CDC class modem, IP packet corruption.
Change-Id: Ib703ed1e226d1d659038f3ebb61674e912ec73c4
Reviewed-on: http://git-master/r/2626
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Tested-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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SPI driver normally enables / disables CPU and bus frequency boost
at the start / end of each SPI transaction. Instead of turning off
frequency boost immediately at the end of each SPI transaction, use
a timeout period after which frequency boost hints will time out.
The timeout period is calculated based on the number of bytes in
the SPI transaction and the SPI clock rate. The timeout insures that
frequency boost is still active in between multiple SPI transactions.
This has the side effect of increasing SPI data transfer rate for
multiple SPI transactions.
This was a cherry-pick from android-tegra-2.6.29
id: I088127ebb5ea07810dac824bfafd3f99ae6c96f2 and
applied to the android-tegra-2.6.32.
Change-Id: I765e892cb34a4fff8d8607cdf52cec065979c6e7
Reviewed-on: http://git-master/r/2338
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Tested-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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The kernel touch stack can support a max of 5 fingers at a time.
Adding support in the driver to suport 5 fingers too. The touch odm
for whistler is broken, hence disable pressure and width support.
Change-Id: I9e148bab2efa0116a6513cc8b1cb2ffc2ea27cc8
Reviewed-on: http://git-master/r/2327
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Moved NvEc calls from nvec-keyboard driver to keyboard odm kit where
all the remaining communication with NvEc resides.
Change-Id: I12c528a7b54a02ccef5129d022934da3476e0fcf
Reviewed-on: http://git-master/r/2471
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Enabling the wakeup keyevent from the GPIOV2. This is required
for the E1206 based board wakeup.
Change-Id: I012d881ea154433cf568ac41a63d02b909672962
Reviewed-on: http://git-master/r/2460
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Change-Id: I7d9bc94317f1c069f124cd9889c27ce22578e50e
Reviewed-on: http://git-master/r/2577
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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since several DMA channels are reserved for the multimedia engine,
restrict block IRQ_MASK_SET to the channels available to the OS
on resume, write the saved IRQ mask value to APB_DMA_IRQ_MASK_SET, not
to APB_DMA_IRQ_MASK
Change-Id: I1e00dc665d93c49f59d75f602e38b67289403a51
Reviewed-on: http://git-master/r/2622
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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fix a couple of typos in the lp0 scratch register mappings
Change-Id: If72859c592011fce8f356553bf1ab1ad8f5d43a7
Reviewed-on: http://git-master/r/2609
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Enabling TOUCHSCREEN_TEGRA_ODM to include touch functionality
in the kernel by default.
Change-Id: Ia964269f395ab869018f7213426d8729dd43153c
Reviewed-on: http://git-master/r/2569
Tested-by: Jitendra Aditya Lanka <jlanka@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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- Added CPU clock divider to saved/restored CPU complex context.
- Made sure flow controller event flag is cleared on resume
- Stopped tegra wake trigger timer after LP2 suspend
Change-Id: I27c5a7d25d4cb4e820836e52fcee152566177edf
Reviewed-on: http://git-master/r/2602
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Changing the Rainbow 570 modem power on pulse time. Rainbow 570 modem requires
power on pulse more than a second. This change increases the power on plus time
and correct the DAP connection table for Rainbow 570. The Rainbow1 modem also
works after the pulse time change.
Bug 640843
Change-Id: I533dbaf89387a38d4ce1aa6a5f98085f79b2abbc
Reviewed-on: http://git-master/r/2522
Tested-by: Szming Lin <stlin@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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To prevent unauthorized access to keys loaded into
key slots in AES engines, disabling read access to
all key slots.
Bug 649783: AES driver must disable read access to keys in all key slots
Change-Id: Id5cd8a059b9b6cef76e4e1817748f84825636d97
Reviewed-on: http://git-master/r/2553
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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It is require to use the hw based CS to meet the timing requirement as:
- Minimum CS setup time i.e. time from CS active to first clock.
- Maximum CS hold time i.e. CS should be active after last clock.
SW based CS can support the above 1 but not 2 because it dpeneds on os
load and system performance. To meet the above requirements, it is
require to enable the hw based CS.
As spi controller support for the hw based CS for the smaller number
of packet, enabling this feature.
Driver use the sw based CS by default. If client want to use the hw
based CS, then it need to enable this through nvodm query
NvOdmQuerySpiDeviceInfo table for different CS.
For this, client need to set device info as
CanUseHwBasedCs = TRUE,
CsSetupTimeInClock = xx
CsHoldTimeInClock = xx
Change-Id: I9e943e0b39f2d75272826cc2ec7687b3434b1c2a
Reviewed-on: http://git-master/r/2536
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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The gma pingroup was not pulled up. doing a pull up of the gma pingroup
reduces the power on the VDDIO_NAND rail by 1.5 mW.
Bug 688283.
Change-Id: I73fcd4bf6ebef66ae4cfc1ffcfeef8bed659b611
Reviewed-on: http://git-master/r/2470
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Added CONFIG_SYSVIPC and CONFIG_SYSVIPC_SYSCTL into harmony and
whistler GNU Linux configuration.
Change-Id: I57db6adf55eecf5b5f7c141c00f1bedb97979d3d
Reviewed-on: http://git-master/r/2532
Tested-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Change-Id: I9bb3607e9605eefd5c0eec07a8be3fafce9bae64
Reviewed-on: http://git-master/r/2528
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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more of the code in this file is tegra power-state specific than common
CPU save and restore routines, so rename it to reflect that it won't
run on non-Tegra SoCs
Change-Id: I22643da41309b48a7f85e62407ec8b7d9f75baff
Reviewed-on: http://git-master/r/2244
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Adding the gpio based keyboard driver support for the E1206 based platform.
The gpio-key driver will get the platform data from odm. The odm will return
gpio pin group information for E1206 based platfrom otherwise return NULL.
The gpio pin information is converted to platform data which will be used by
the gpio key driver.
Change-Id: I9fd34f82abef86157a92aabcb01cc3ebe0059886
Reviewed-on: http://git-master/r/2420
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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in both LP0 and LP1, SDRAM is placed into self-refresh. in order to safely
perform this transition, the final shutdown procedure responsible for
* turning off the MMU and L1 data cache
* putting memory into self-refresh
* setting the DDR pads to the lowest power state
* and turning off PLLs
is copied into IRAM (at the address TEGRA_IRAM_BASE + SZ_4K) at the
start of the suspend process.
in LP1 mode (like LP2), the CPU is reset and executes the code specified
at the EVP reset vector. since SDRAM is in self-refresh, this code must
also be located in IRAM, and it must re-enable DRAM before restoring the
full context. in this implementation, it enables the CPU on PLLP, enables
PLLC and PLLM, restores the SCLK burst policy, and jumps to the LP2 reset
vector to restore the rest of the system (MMU, PLLX, coresite, etc.). the
LP2 reset vector is expected to be found in PMC_SCRATCH1, and is
initialized during system-bootup
in LP0 mode, the core voltage domain is also shutoff. as a result, all
of the volatile state in the core voltage domain (e.g., pinmux registers,
clock registers, etc.) must be saved to memory so that it can be restored
after the system resumes. a limited set of wakeups are available from LP0,
and the correct levels for the wakeups must be programmed into the PMC
wakepad configuration register prior to system shutdown. on resume, the
system resets into the boot ROM, and the boot ROM restores SDRAM and other
system state using values saved during kernel initialization in the PMC
scratch registers
for simplicity, the outer cache is shutdown for both LP0 and LP1; it
is possible to optimize the LP1 routine to bypass outer cache shutdown
and restart
v2 fixes from Vik Kasivajhula:
* restore PLLC during LP1 resume
* fix typo which set the CPU clock burst policy to PLLM, rather than PLLP
Change-Id: Icb1d2cbcbac8503369a10d16fd5c8b561af5a35a
Reviewed-on: http://git-master/r/1773
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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to restore from LP0, a large number of memory, arbitration and PLL
settings need to be preserved in scratch registers in the AO domain
for the boot ROM to reload them after exiting LP0.
Change-Id: Ic446ef47c3cba9b792dd7b86b176157757504bde
Reviewed-on: http://git-master/r/2154
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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outer_restart should be called by platform suspend_ops to restore
the outer cache to an active state following a power transition
which disables or otherwise invalidates the outer cache state.
Change-Id: I07a5268d1783fecd36491138e20913fca24a26d9
Reviewed-on: http://git-master/r/2243
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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CHAN_STA is the interrupt status register (write-to-clear), so preserving
it across power transitions doesn't make a lot of sense
Change-Id: Ibf4d6da17da5afbbde7572295207844cca63d38a
Reviewed-on: http://git-master/r/2516
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Enabling the gpio key config to enable the functionality of gpio based
key driver for the E1206 based platform.
Change-Id: I9296051993a8e93034cc3a90edf988a1df9a5925
Reviewed-on: http://git-master/r/2459
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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- Clearing dma buffer after ECB operation
- Removed acquisition / releasing of hardware lock in AesCoreEcbProcessBuffer.
Change-Id: I942d1758ef08af2b3bd0c2d72207a90daeffba20
Reviewed-on: http://git-master/r/2416
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Skipped spare clock h/w access when DVFS is running - it was not used,
anyway, since all rates in this case are available in DVFS variables.
Change-Id: Id324c7904e30ea8fe50b319cfd06c75a721b6b3f
Reviewed-on: http://git-master/r/2458
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Change-Id: I56e56dc8ad7d848be8363845dff5bd48a7e4fe38
Reviewed-on: http://git-master/r/2507
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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This is a port of change 1465 from android-tegra-2.6.29.
Change-Id: Ibca32ecc0424fae28e4db04977722f7d7a6c6938
Reviewed-on: http://git-master/r/2502
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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