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2011-05-17arm: config: Removing DUMMY REGULATOR from cardhu/ventana/enterpriseLaxman Dewangan
Removing the config variable REGULATOR_DUMMY from cardhu, ventana and enterprise as these boards have actual regulator. Change-Id: Ia39478b6adf887ca247cbf34bd8618b8ad463239 Reviewed-on: http://git-master/r/31136 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-17ARM: tegra: power: Add suspend index to cpufreq tableAlex Frid
Change-Id: I7bbe018f3786b9683cc9d4189fdcaadb9098f3f1 Reviewed-on: http://git-master/r/31456 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-17ARM: tegra: power: Update Tegra3 CPU DVFS tableAlex Frid
Change-Id: I3164bb2d86619b891a647b5e6550470c509eb403 Reviewed-on: http://git-master/r/31308 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-05-17ARM: tegra: power LP0/LP1 selection via sysfsKaran Jhavar
Select LP0/LP1 on runtime using sysfs node /sys/power/suspend/type. Valid selctions/commands are: 1. lp0 2. lp1 3. lp2 Change-Id: I335a8845dbfed7539ae4bf8aee3ba3b97ecb3db3 Reviewed-on: http://git-master/r/30081 Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2011-05-17ARM: tegra: clock: Enable clock while setting rate/parentAlex Frid
When clock configuration (source mux, divider value) changes, the new control register setting does not take effect if clock is disabled. Later, when the clock is enabled it would run for several cycles on the old configuration before switching to the new one. This h/w behavior creates two problems: - since dvfs takes into account only new (enabled) rate, the module can be over-clocked during initial phase of the clock switch - since parent clock refcount is updated when the mux register was written, the parent clock maybe disabled by the time of actual switch and h/w would not be able to complete switch at all To avoid described problems clock is now always enabled while setting the new rate/parent (and disabled afterwards to keep refcount intact). Change-Id: I9bda56a2a98c9f3678715da1e1b8fe78874fb71e Reviewed-on: http://git-master/r/31640 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-17ARM: 6355/1: hw-breakpoint: add mechanism for hooking into prefetch abortsWill Deacon
On ARM processors with hardware breakpoint and watchpoint support, triggering these events results in a debug exception. These manifest as prefetch and data aborts respectively. arch/arm/mm/fault.c already provides hook_fault_code for hooking into data aborts dependent on the DFSR. This patch adds a new function, hook_ifault_code for hooking into prefetch aborts in the same manner. This is picked from following git repository: git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-2.6.38.y.git Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: S. Karthikeyan <informkarthik@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> (cherry picked from commit 3a4b5dca53aecb16db9e007d782b2d1e757e941a) Change-Id: Ic278bad0e3bb95f504e46b216a8d14fd61fbc4a5 Reviewed-on: http://git-master/r/31574 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-17mach-types: Official tegra_enterprise machine numDan Willemsen
http://www.arm.linux.org.uk/developer/machines/list.php?id=3512 Change-Id: I432bd8512025c6f3ff312b8e120df37c68aa1153 Reviewed-on: http://git-master/r/31409 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
2011-05-13ARM: tegra: power: PM269: Add GPIO_REGPradeep Goudagunta
Adding GPIO_REG for power rails of PM269 board. Bug 823160 Change-Id: Idbb889420e033780900b1b1b700637017640414e Reviewed-on: http://git-master/r/30366 Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13ARM: tegra : power: Set power rails SATA & PCIE off by defaultKaran Jhavar
Setting SATA & PCIE power rails (ldo1 & ldo2) off by default since they are not enabled on Cardhu. Bug 793780, 790141 Change-Id: If905f156b99314271874536d61fe384715f2412a Reviewed-on: http://git-master/r/31292 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13ARM: tegra: enterprise: use UART4 as debug uartPradeep Goudagunta
Enable UART4 as debug uart. Bug 814271 Bug 822432 Change-Id: I73f01191d5f1e0fe979eb804028e0a7956eb93df Reviewed-on: http://git-master/r/30513 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13arm: tegra: nvmap: Forcing to convert CarveOut requests to IOVMHiro Sugawara
Adding a build time CONFIG option to enable forcing of conversion of non-IRAM CarveOut memory allocation requests to IOVM requests. Default is "y" to force the conversion. Each forced conversion is reported to console. Allocation alignments larger than page size for IOVM are enabled. Single page CarveOut allocations are converted to system memory. CarveOut memory reservation has been removed for aruba, cardhu, and enterprise. Change-Id: I3a598431d15b92ce853b3bec97be4b583d021264 Reviewed-on: http://git-master/r/29849 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13video: tegra: dsi: Adjusted the values of packet sequence registers.Kevin Huang
Changed the values of packet sequence registers for DSI burst video mode. Change-Id: I70188ed3c8fff094862a89377457751fd0d4382c Reviewed-on: http://git-master/r/31080 Reviewed-by: Kevin Huang <kevinh@nvidia.com> Tested-by: Kevin Huang <kevinh@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13ARM: defconfig: Cardhu: Enabling ARM erratasvenu byravarasu
Enabling arm erratas 743622, 751472 and 752520 for cardhu Change-Id: I0fb985a6bc78160683924875f14b2afbecba0604 Reviewed-on: http://git-master/r/31473 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-05-13media: tegra: avp: Use SMMU to load AVP kernelKaz Fukuoka
- Use nvrm_avp_e0000000.bin is for Tegra3 A01 - Use nvrm_avp_00001000.bin is for Tegra3 A02 and later bug 765965 Change-Id: I9bc28b122bd1b0cd2c1ece3bc681550de5912229 Reviewed-on: http://git-master/r/31202 Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com> Tested-by: Kaz Fukuoka <kfukuoka@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
2011-05-13ARM: tegra: power: Limit Tegra3 CPU nominal voltageAlex Frid
Limit Tegra3 CPU nominal voltage in case when maximum rate specified in the clock tree is below maximum rate in CPU dvfs table. Change-Id: Ie7b47a1f482f3c33da19e530b05663683bd807a1 Reviewed-on: http://git-master/r/31307 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-05-13ARM: tegra: clock: Support Tegra3 CPU clock fractional dividerAlex Frid
Added support for Tegra3 CPU super-clock fractional 7.1 divider: use it to adjust CPU rate, when super-clock parent is fixed rate PLL (for other parent PLLs with adjustable frequency set divider 1:1). Bug 821438 Change-Id: Ib8342330d103beb535af4d74ea51c46b9e25dc30 Reviewed-on: http://git-master/r/31219 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-05-13arch: arm: tegra: Bringup Enterprise touchscreen.Alex Odorovic
Bug 824702 Change-Id: I9eb48dee19b3d9e37843a83ee28e9ffb008ddd7e Reviewed-on: http://git-master/r/31077 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Aleksandar Odorovic <aodorovic@nvidia.com> Tested-by: Aleksandar Odorovic <aodorovic@nvidia.com>
2011-05-13ARM: tegra: power: Add out-of-range CPU dvfs entryAlex Frid
Change-Id: Ic50e6261e34caa3851ef68a6e2a6cbbd600a13d6 Reviewed-on: http://git-master/r/30929 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-05-13ARM: tegra: power: Set Tegra3 CPU/core rail nominal voltageAlex Frid
For different Tegra3 process corners/skus/revisions/boards set nominal voltages for CPU and core rails as well as adjust maximum clock rates as follows. - VDD_CORE rail nominal voltage: default value is indexed by speedo_id of the chip (speedo_id is determined by chip sku and revision). Minimum of the default and board specific electrical design voltage is rounded down against core dvfs voltage ladder. The result is set as nominal core voltage (edp voltage API is not implemented, yet). - VDD_CPU rail nominal voltage: default value is indexed by speedo_id of the chip. If too high, it is lowered to core nominal voltage so that core_on_cpu dependency is resolved at nominal core level. The result is compared with voltage required to reach CPU maximum rate as specified in the dvfs table for the particular process corner. Again, the minimal level is selected, and finally set as CPU nominal voltage. After nominal voltages are determined, maximum rate for each dvfs clock is adjusted accordingly, so that it does not exceed the rate specified in the respective DVFS table at nominal level. Change-Id: Ia6c1c5c853f98ab185f42bf1cfd7a1d7d54d10c3 Reviewed-on: http://git-master/r/30928 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-05-13ARM: tegra: enterprise: sdhci: Initial changesPradeep Goudagunta
Enterprise board uses SDMMC3 slot for External SD and SDMMC1 slot for WiFi. Bug 822432 Change-Id: Ifa13d69fa65f974c8457b9ffec231579b356a810 Reviewed-on: http://git-master/r/30514 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
2011-05-13arm: tegra: Exposing more i2s port for Baseband.Vinod G
Exposed the baseband i2s port for cardhu. Added separate audio init function. Change-Id: I9ff38f101c5540ad6e2365ed93a8c88373164ea3 Reviewed-on: http://git-master/r/30087 Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
2011-05-13nvhost: Add tracing to nvhost driver.Terje Bergstrom
Creates /d/tracing/events/nvhost. Logs channel opens, closes, writes and flushes. For writes, logs number, size and address of cmdbufs and number of relocs. Change-Id: I5bdadcb40c31e3f057eb8c4579b95e235d860e39 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/29770 Reviewed-by: Andrew Howe <ahowe@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
2011-05-11ARM: tegra: usb_phy: Fix USB compilation warningsRakesh Bodla
Removing unused variable. Change-Id: Idf5fd40c7a953505c08872023b3d55296237ec49 Reviewed-on: http://git-master/r/30690 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11arm: tegra: cardhu: Adding platform data for sh532u deviceLaxman Dewangan
Adding the board init and deinint function to power on/off rails for the sh532u autofocus driver. This function is passed as platform data to the driver. bug 802264 Change-Id: Ib7ef55898dce5f6ae458c922e6b5cbce64740cd0 Reviewed-on: http://git-master/r/30171 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11ARM: tegra: power: put IO_PAD to DPD during suspendJin Qian
Bug 814805, 767218 Change-Id: I818ebde2f7fd45152d1229ec257aa5f177d5253f Reviewed-on: http://git-master/r/30108 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11ARM: defconfig: Enable UVC USB camera supportYuvraj Pasi
Enable UVC driver to support the UVC usb camera. Disable usb suspend because if we enable it if fails to detect the usb camera sometimes. Bug 801763 Change-Id: I790739362a89ad04dbd356550a11a3920af12fde Reviewed-on: http://git-master/r/30025 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11arm: tegra: cardhu: Adding cam-AF power railsLaxman Dewangan
Adding the camera autofocus power rail infomration. Removing non-existant peripheral entry from i2c4 bus. Adding deselect mux option after each i2c transfer through mux i2c. bug 802264 Change-Id: Id87178666e4d8c4c5db3f8be708fc5fc85b3e2e4 Reviewed-on: http://git-master/r/29998 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11arm: tegra3: pinmux: Removing HDMI option from LCD_SCK/PWR0Laxman Dewangan
Removing the HDMI pinmux from pingroups LCD_SCK and LCD_PWR0 as per TRM document. Change-Id: I85e3a5fb3af1cecbe6eb83d47e811362cd4ee629 Reviewed-on: http://git-master/r/29970 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11ARM: errata: 727915: Background Clean & Invalidate by Way operation can ↵vdumpa
cause data corruption. PL310 implements the Clean & Invalidate by Way L2 cache maintenance operation (offset 0x7FC). This operation runs in background so that PL310 can handle normal accesses while it is in progress. Under very rare circumstances, due to this erratum, write data can be lost when PL310 treats a cacheable write transaction during a Clean & Invalidate by Way operation. This fix is to replace the background Clean & Invalby Way operation by a software loop on all sets/ways. This works for r2p0 and r3p0 as well. Change-Id: I45e841d8049a18f2dd36ce13e8ef15322f14c5d5 Reviewed-on: http://git-master/r/29690 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11ARM: defconfig: enabling PMU RTC on Cardhuvenu byravarasu
Enabled TPS6591x PMU RTC & disabled Tegra internal RTC Change-Id: I480ad99646b8eb57928a0b9c4d17fa0d6ed81d40 Reviewed-on: http://git-master/r/29636 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11ARM: tegra: restore voltage to nominal when rebootBo Yan
At the time of reboot, all rails need to be set to nominal to ensure the success of subsequent boot. bug 821969 bug 797082 Change-Id: Iee635c222619dfcb3e98f13e665ea2bd04e94245 Reviewed-on: http://git-master/r/30086 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11arm: tegra: ventana: deselect pca9546 i2c mux channel on exitNitin Kumbhar
On ventana, pca9546 is used as a mux for 0v2710/ov5650 camera sensors. With UJA0H14 version of ov5650 sensor, it is observed that pca9546 driver incorrectly caches last channel when VDDIO_CAM is toggled while enabling/disabling tegra camera. Deselect i2c mux channel on exit so that i2c mux is correctly configured with new mux channel. BUG 812134 (cherry picked from commit 2d62e589c0bd933db846d4b8f9fe4f2116bef8ad) Reviewed-on: http://git-master/r/29811 (cherry picked from commit c53b7eb26bee96fd7927e94848055af94baa831b) Change-Id: Ic41a952d05b610e569e37802cf05552af9d93e13 Reviewed-on: http://git-master/r/30975 Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-05-11arm: tegra: Support for core_edp and panel type from kernel command.Laxman Dewangan
Selecting the core EDP voltage and panel type from the kernel commands. The bootloader pass this information through kernel command. Board will select the default configuration if there is no command option for these parameters. bug 822053 Change-Id: Id7909d70b599c4a313d60d3ba2a9cf5b9eb7f2c3 Reviewed-on: http://git-master/r/30853 Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-05-11arm: tegra: fix aruba build breakVinod G
Change-Id: I7b267a813a2db39704ea8632d3b9c93df6a51379 Reviewed-on: http://git-master/r/30558 Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
2011-05-11ARM: tegra: power: Update Tegra3 core DVFS tablesAlex Frid
Updated Tegra3 core DVFS tables with characterization results. Changed default maximum limits for: sdmmc2/4 to 104MHz, vi to 300MHz, and hdmi to 148.5MHz. Change-Id: Icd07d933d7d2f8c77d6e023b19b62e7ee3fc775a Reviewed-on: http://git-master/r/30551 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-05-11ARM: tegra: fuse: fix sysfs programming/reading logicVarun Wadekar
some testing revealed certain loopholes in the code. also the way the shell sends data down to the sysfs handlers changed which warranted the change in the handlers. Original change: http://git-master/r/#change,30134 (cherry picked from commit 64671e8dd11779b04e71048551cabfa8b04e3bb9) Change-Id: Iccd02bd5a257312fd8ef764980005edaf28db0a7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/30454 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-05-11ARM: tegra: power: restore ARM errata fixes after cpu power/rail gating.vdumpa
Bug 804805 Change-Id: I040ae5888a8e013d8e57bfdd56f59af25607c77c Reviewed-on: http://git-master/r/30413 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-11ARM: tegra: implement events for clock tracingPeter De Schrijver
Change-Id: If6ae23251aa615a678c8edb76d3c1e6463d86f2e Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Change-Id: I50ffa54eacaf5b3973fcd6cb94eee56e46ec81bf Reviewed-on: http://git-master/r/30384 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-11ARM: tegra: cardhu: Separate LPDDR2 processor boardAlex Frid
Made sure default DDR3 EMC DFS table is not applied to cardhu processor board with LPDDR2. Change-Id: I78bb2a4f80a5db00e04cb82c530924219e6baa78 Reviewed-on: http://git-master/r/30311 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
2011-05-11ARM: tegra: clock: Limit Tegra3 fractional divisors usageAlex Frid
Per Tegra3 characterization results, do not use fractional ratios for dividing host1x/3d/2d/epp/mpe/vi/vde/se clocks. Also prevent using 1:1.5 ratio by system clock dividers (other fractional ratios are still allowed for sclk). Change sclk rounding algorithm to round up divider ladder, since sclk shared bus clock should honor maximum shared user request. Bug 803144 Change-Id: I7b4bb1bb21a4ce4bbfb958c9a603a868dc3c05b4 Reviewed-on: http://git-master/r/29937 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-05-11ARM: tegra: power: Add Tegra3 CPU/CORE rails dependenciesAlex Frid
On Tegra3 VDD_CPU must be within [VDD_CORE - 300, VDD_CORE] range. Updated tegra dvfs accordingly, and resolved circular dependencies between CPU and CORE rails created by this requirement. Change-Id: I9c332ca2b4f4ed1599cb0712eb3eca55a1fa1539 Reviewed-on: http://git-master/r/29935 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-05-11tegra: cardhu: Set smartdimmer to disable by default.Laurence Harrison
Now that we have sysfs objects for smartdimmer, set our default to disable for this feature. Change-Id: Ie5a6755ff159496fe0e02a3f164325672954712d Reviewed-on: http://git-master/r/29892 Reviewed-by: Laurence Harrison <lharrison@nvidia.com> Tested-by: Laurence Harrison <lharrison@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-05-11ARM: tegra: power: speedo, cpu, core process ids for tegra3Diwakar Tundlam
Change-Id: If206f26e0f10f666fd7839c1ebb839eeb4899e21 Reviewed-on: http://git-master/r/29879 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-11arm: tegra: cardhu: Unused pins from vddio_gmi to low power modeLaxman Dewangan
Configuring the pins which are belonging to vddio_gmi to recommended state to consume low power. bug 807813 Change-Id: I18b67688b0e45ccd5f16ac3f1f8a7f4db3142bae Reviewed-on: http://git-master/r/29628 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-11ARM: tegra: enterprise: sdhci: Build FIXPradeep Goudagunta
Build Fix. Bug 822432 Change-Id: Ia9d2d3ddc9aa9b2c00761ceb30a2bdcda8d261cf Reviewed-on: http://git-master/r/30718 Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
2011-05-11arm: tegra: usb_phy: ulpi fix for tegra_3x_socNitin Kumbhar
Change-Id: Ia7155f3e94c127b18f2909f9f80583e5f74b8483
2011-05-11Merging android-tegra-2.6.36 into git-master/linux-2.6/android-tegra-2.6.36Nitin Kumbhar
Conflicts: arch/arm/mach-tegra/usb_phy.c drivers/usb/gadget/fsl_tegra_udc.c drivers/usb/host/ehci-tegra.c drivers/video/tegra/dc/dc.c Change-Id: I62d72b8b96d4039bd0d253583c415ae714fb2693
2011-05-10Revert "arm: tegra: cardhu: Setting the gpio pins properly."Jin Qian
Original change breaks LP1 on t30. This reverts commit 522f94b14b99c47322a72012fb5ce9a59c145630. Change-Id: Ia3aacc5924987828aa0fd1e2c6ccc3c990b871c0 Reviewed-on: http://git-master/r/31023 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-10Revert "ARM: defconfig: enabling vibrator on Cardhu"Jin Qian
Original change breaks LP1 on t30. This reverts commit b7e127ac1a4dbfd1fd66f02f8e0c7ac40e732674. Change-Id: I337c03a7f927a54f96b502beebd1a580e469624d Reviewed-on: http://git-master/r/31022 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-06ARM: tegra: Fix wait_util race/very long wait.Alex Frid
Change-Id: I782ca4ffc94175e5e73535fbb0309173a72a83d5 Reviewed-on: http://git-master/r/30582 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-12-29 13:43:46 +0000