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Board file for Synaptics SPI touch connection which is
used for DirectTouch initialization
Bug 912775
Reviewed-on: http://git-master/r/74643
Change-Id: Ie296ddff5b9e1fbf9296d40fde2877598a13207e
Signed-off-by: Peter Zu <pzu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77775
Reviewed-by: Automatic_Commit_Validation_User
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Board file for Raydium SPI touch connection which is
used for DirectTouch initialization
Bug 832605
Reviewed-on: http://git-master/r/74618
Change-Id: Icac5ebd22b5a3b6fe38d3e23a37f88df067c0c10
Signed-off-by: Peter Zu <pzu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77773
Reviewed-by: Automatic_Commit_Validation_User
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Added Tegra3 MSelect clock to memory on CPU clock dependencies:
MSelect rate is scaled as half of CPU rate, up to 102MHz. Prevented
CPU clock increase if updates of dependent clocks (EMC and MSelect)
have failed.
Reviewed-on: http://git-master/r/76485
Change-Id: I679b60eb5aa13d5cca2b9751ff2c8c2fb866a076
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77767
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Added clock for memory path selection module (MSelect) to Tegra3
peripheral clocks. Initialized MSelect clock rate to 102MHz.
Reviewed-on: http://git-master/r/76484
Change-Id: I73676882d8e6805445985b23257bcf6410e8c3e0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77766
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Re-enable usb auto suspend on system resume by making
get_interface() and put_interface() calls.
BUG 921565
Reviewed-on: http://git-master/r/73468
Change-Id: Ieb7c82e73a7134e1d3bb8b0b3e96a42ed6672afe
Signed-off-by: Seshendra Gadagottu<sgadagottu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77763
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Reviewed-on: http://git-master/r/77216
Change-Id: I1a9183102bcb1c70956f773101b2cf78c4dc2fc9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77758
Reviewed-by: Automatic_Commit_Validation_User
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sysfs interface to select suspend mode as TEGRA_SUSPEND_NONE
is disabled. Additionally, if tegra_suspend_dram is called
with suspend mode as TEGRA_SUSPEND_NONE we return error
bug 927937
Reviewed-on: http://git-master/r/77268
Change-Id: Ifdd57cdf27e739a9c093cad4eddefb73a6a2355d
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77757
Reviewed-by: Automatic_Commit_Validation_User
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Clock audio from clkm as
a pre-condition of disabling pllp_out1 and plla
when I2S is in slave mode.
Change-Id: I1706c2989cf7ad9045526ceba3326777b702868a
Reviewed-on: http://git-master/r/76391
Signed-off-by: ScottPeterson <speterson@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I243508cc553ebf22bb5594a9461019abfec24b65
Reviewed-on: http://git-master/r/77753
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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tegra2_cpu_set_resettable_soon() should be called in CPU1 only.
Reviewed-on: http://git-master/r/75517
Change-Id: I0825a2d2ed2935d2b1dac1ff7d134e1f4f37f552
Signed-off-by: Joshua Cha <joshuac@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77751
Reviewed-by: Automatic_Commit_Validation_User
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Correcting the strobe and SOFs behaviour. This avoids run-stop
bit to start before actual bus_reset. Also, pullup the
strobe signal during idle and wait for connect detect
after bus idle.
Bug 898008
Bug 922444
Reviewed-on: http://git-master/r/73261
Change-Id: I01999521013677f159ee9c12f2d7bcb453c3b39d
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77748
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-on: http://git-master/r/75209
Change-Id: I4c90973c808bb9f21a01d6d30fd1bfe915728439
Signed-off-by: Joshua Cha <joshuac@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77747
Reviewed-by: Automatic_Commit_Validation_User
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Check the state machine before poweron the modem by device
attribute change routine. Maintain the state machine to
avoid crash after writing state change to
/sys/devices/platform/baseband_xmm_power/xmm_onoff
Also cancel workqueue at module unload to avoid
possible crash.
Bug 898008
Reviewed-on: http://git-master/r/72934
Change-Id: I0d8286774040f155c930ecb0bb69778de6c606ac
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77744
Reviewed-by: Automatic_Commit_Validation_User
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Use the parameter name and value to set to the conservative
governor.
Also defined the value of freq_step to be 3 and set it during
early suspension.
Bug 922351
Reviewed-on: http://git-master/r/73841
Change-Id: Ieefa487f8b255d4bf242a7d98b07dc3758a70e86
Signed-off-by: Wen Yi <wyi@nvidia.com>
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77743
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Instead of using sdmmc3_vdd_sel as a fixed regulator, convert it
to a gpio-regulator.
Change-Id: I459f9a4afc4b7dd3f6f2147483b938887764d355
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77742
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-on: http://git-master/r/76691
Change-Id: I0134c46c5fceb1ee863f97a6b6e1aed9608b842f
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77739
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Reviewed-on: http://git-master/r/76686
Change-Id: I88939c92aa1c28f5177010ba2afd524c3a4b713d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77738
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-on: http://git-master/r/76692
Change-Id: Iaf9e52fd84f91ad275e1836eda5417c5bd70db02
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77737
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Disable unused pll_p_out clocks until they are
needed to reduce power.
Reviewed-on: http://git-master/r/76778
Change-Id: I16dba325fff48cc895ec115f3a4124a1d7228cee
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77736
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Move gpio regulators into their own table to avoid incorrect cast in
fixed regulator initialization function.
Reviewed-on: http://git-master/r/76761
Change-Id: If98790dc843d7e1d7201a62f4977e15ae18502ca
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77735
Reviewed-by: Automatic_Commit_Validation_User
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tegra_pll_c_freq_table had an error in the output clock rate. This patch
fixes it so that the formula o =(i * (n / m)) holds true.
Bug 917377.
Reviewed-on: http://git-master/r/76943
Change-Id: I06cb132e9ac05dac905ef2ef0437f5278cf916e5
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77734
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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for low driver strength of daps we are getting noise in voice call
hence increase the drive strength of daps for voice call
Bug: 919350
Change-Id: I29dca68f339078cd80bebdb6ae46b46117e32949
Reviewed-on: http://git-master/r/77002
Change-Id: I4c59379a1859938038cff175ab695808bddb0963
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77733
Reviewed-by: Automatic_Commit_Validation_User
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Enable Raydium touch touch driver which is used for
DirectTouchpurposes.
bug 832605
Reviewed-on: http://git-master/r/76385
Change-Id: I633291cf5e11d66709f224292d02e211cca051fd
Signed-off-by: Peter Zu <pzu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77728
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Limited carveout memory gives Out of Memory errors for
1080p camera preview. Even when camera app runs 640x480
preview carveout memory almost all of carveout memory
(127/128) gets used.
bug 907782
bug 911767
Reviewed-on: http://git-master/r/69492
Change-Id: I993d656910a1853f22719411553dbec3edb9f53f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77311
Reviewed-by: Automatic_Commit_Validation_User
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Bug 896827
Reviewed-on: http://git-master/r/75867
Change-Id: Id37fe5557f6d7993f6df424d0a8d027acb6bd1b4
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77310
Reviewed-by: Automatic_Commit_Validation_User
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Section mismatch warning messages were due to declaring tegra_pcie_hw using
__initdata & tegra_pcie_scan_bus using __init.
Hence removed them.
bug 929358
Reviewed-on: http://git-master/r/76495
Change-Id: I1894c1c360e0fc0f3da18bbe840e88afa4de6ffc
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77308
Reviewed-by: Automatic_Commit_Validation_User
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Disabled dpd support for all SD instances - SDMMC0, SDMMC2 and SDMMC3
bug 924452
Reviewed-on: http://git-master/r/76275
Change-Id: Id8967ccb79fc87fcb249c2a2085cd9d68e1ffcb8
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77304
Reviewed-by: Automatic_Commit_Validation_User
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regulator vdd_vbus_micro_usb is not yet defined.
remove it to fix kernel boot failure
Reviewed-on: http://git-master/r/76253
Change-Id: If2efc8efab70fcc130f9303ac6a04428c8e4489b
Signed-off-by: Peter Zu <pzu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77301
Reviewed-by: Automatic_Commit_Validation_User
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Bug 913259
Change-Id: Id337b7d9c24ee226e3de5f38dc495e03084a4ba0
Reviewed-on: http://git-master/r/74830
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Signed-off-by: Peter Zu <pzu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77299
Reviewed-by: Automatic_Commit_Validation_User
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Register PMU MAX77663 and provide detailed power rails information.
Change-Id: I28051b621b72c88519c57ba2485fa7cdb4e76c70
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Icace4430f24c7e3ac62ed2ac359ace707cd11209
Reviewed-on: http://git-master/r/77298
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-on: http://git-master/r/74496
Change-Id: Icc6316ddddd1e6a7e9634a6539ae48cbbcd87607
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77297
Reviewed-by: Automatic_Commit_Validation_User
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Create initial board files and config files for Kai.
Reviewed-on: http://git-master/r/74441
Change-Id: I4b07607da85fe4bcb00e5fce2ddbc2a83471b1de
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77296
Reviewed-by: Automatic_Commit_Validation_User
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Tegra3 platform may boot with one of the predefined fixed PLLP
(peripheral PLL) output rates: 216MHz, 408MHz, or 204MHz. This
commit implements auto-detection of PLLP rate, as well as CPU,
and system bus PLLP dependencies configuration during clock tree
initialization.
Bug 928260
Change-Id: I65ea4db2e5cfe96f13566c93e882a3be9deaa129
Reviewed-on: http://git-master/r/75850
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77295
Reviewed-by: Automatic_Commit_Validation_User
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Tegra3 platform may boot with one of the predefined fixed PLLP
(peripheral PLL) output rates: 216MHz, 408MHz, or 204MHz. This
commit implements auto-detection of PLLP rate, and debug uart
configuration during kernel uart initialization.
Bug 928260
Change-Id: I3fac4c462f28ac3dc1c72c0cc0f8f87fa0a809c4
Reviewed-on: http://git-master/r/75849
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77294
Reviewed-by: Automatic_Commit_Validation_User
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Tegra3 platform may boot with one of the predefined fixed PLLP
(peripheral PLL) output rates: 216MHz, 408MHz, or 204MHz. This
commit implements auto-detection of PLLP rate, and debug uart
configuration during kernel uncompressing.
Bug 928260
Change-Id: I435c228691191434a10847fdbccef048a8d507c7
Reviewed-on: http://git-master/r/75848
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77293
Reviewed-by: Automatic_Commit_Validation_User
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remove CAM3_LDO_SHUTDN_L_GPIO as it is not connected.
Bug 925547
Change-Id: Ide685bd5ee4773e5b3f3cbaf1c938de57c621764
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/76996
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
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Not used in tegra. With it, the driver continously
spews on console.
Bug: 930042
Change-Id: I6394c1ee1de19bc114006f064d12b987b499d8a6
Reviewed-on: http://git-master/r/#change,61354,patchset=2
(cherry picked from commit 838d4ba231e5bd550114f89cf92c75391416df3b)
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Signed-off-by: Preetham Chandru <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/76969
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Add WAR to fix 2LS voilation during usb remote resume.
Bug 880538
Reviewed-on: http://git-master/r/75845
Change-Id: I552c9e657776f67c263ef750a7786c796dc785cb
Signed-off-by: Venkat Moganty <vmoganty@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76822
Reviewed-by: Automatic_Commit_Validation_User
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Removed tsensor initialization if external tdiode is
being used for temperature measurements.
bug 928188
Reviewed-on: http://git-master/r/75995
Change-Id: Ifcfd5b4c2b094dcd4fb5386708b332f2a76c272c
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76819
Reviewed-by: Automatic_Commit_Validation_User
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Add backup clock source option in dc platform configuration. Use
backup source if fixed frequency pllp is specified as main source,
but its rate can not be divided into pixel clock within required
tolerance.
928260
Change-Id: I19bd9173276c6ea087f86361956809787875e979
Reviewed-on: http://git-master/r/76033
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76818
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-on: http://git-master/r/76065
Change-Id: I8eb5148399cc8a08c2f37f20927b655f3e909241
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76817
Reviewed-by: Automatic_Commit_Validation_User
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Since not all possible PLLP output rates (216MHz, 408MHz or 204MHz)
can provide accurate enough pixel clock rate for cardhu panel, use
PLLD2 as backup clock source.
Bug 928260
Change-Id: I767e621606e849cb7d1976fbed198b9427660544
Reviewed-on: http://git-master/r/76034
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76816
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Added locking for non-atomic access to shared registers for the
following clocks:
- secondary PLL dividers
- audio doublers
- cml (sata/pcie) clock controls
Added locking for peripheral clocks secondary reference counting
(register access is atomic, but some clocks may share an enable bit).
Updated comments for external output clocks (shared access already
protected).
Reviewed-on: http://git-master/r/76163
Change-Id: If656bf13d966bf4590d55c5509860110efea937b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76814
Reviewed-by: Automatic_Commit_Validation_User
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Modify kernel config flags in tegra3_defconfig and
tegra_defconfig to build the camera drivers as modules.
Bug: 928498
Change-Id: I516618c25e5790dc270a97579a9852c442821eaf
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/76787
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Enable CONFIG_SENSORS_NCT1008
Change-Id: I855e68dc30f73ea0e2c7f1c0b1cfbb11a1f8b0e9
Signed-off-by: Wei Ni <wni@nvidia.com>
Reviewed-on: http://git-master/r/75903
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Tegra 20 IOMMU H/W, GART (Graphics Address Relocation Table). This
patch implements struct iommu_ops for GART for the upper IOMMU API.
This H/W module supports only single virtual address space(domain),
and manages a single level 1-to-1 mapping H/W translation page table.
Change-Id: I2f550bf0e14d9f994abdde79b835ddfe815faa5a
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/75945
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Because of incorrect struct member name. This is the left over from
the previous commit.
Change-Id: Ia4a824761bce69ad8f740ed7525c58affca7d1fb
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/75281
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Check for valid clock after setting up phy
in UTMIP reset
Bug 853708
Bug 886080
(reviewed on http://git-master/r/51555)
(cherry picked from commit 25b340b64ca27971f6d2d555299a749f0394e77e)
Change-Id: I98c79fb1e8961b9af19f3001fe6fbde2b28509a0
Reviewed-on: http://git-master/r/75502
Reviewed-by: Simone Willett <swillett@nvidia.com>
Signed-off-by: Ken Chang <kenc@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76468
Reviewed-by: Automatic_Commit_Validation_User
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Using fixed regulator in place of gpio-switch regulator.
Fixed regulator is very similar to gpio-switch regulator
and it is available by default in linux kernel.
gpio-switch-regulator will be used only for the open
collector load switches.
bug 923713
Change-Id: I42480cb314135d475b4d4b56bb5e8e73eba2f77e
Reviewed-on: http://git-master/r/74536
Reviewed-by: Simone Willett <swillett@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76465
Reviewed-by: Automatic_Commit_Validation_User
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need to support negative values for usb calibration.
change xcvr_setup_offset from unsigned to signed.
bug 872648
(cherry picked from commit 06258b46589436b5579c8265405b1cb286c406aa)
(reviewed on http://git-master/r/66101)
Change-Id: I1ab6a63184fe48bc734152546a541085ac7c6efc
Reviewed-on: http://git-master/r/74503
Reviewed-by: Simone Willett <swillett@nvidia.com>
Signed-off-by: Ken Chang <kenc@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76464
Reviewed-by: Automatic_Commit_Validation_User
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- Expanded Tegra3 DVFS tables with 0.95V core voltage step
- Updated cbus minimum rate calculation, since cbus can not
run at 0.95V
- Updated PLLM dvfs initialization, since PLLM can no longer
be voltage independent, even when its usage is restricted.
Bug 817679
Bug 841336
Change-Id: I4973dc19d351ce237f2b249ebf75a79abf3afef4
Reviewed-on: http://git-master/r/74141
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76463
Reviewed-by: Automatic_Commit_Validation_User
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