linux-toradex.git - Linux kernel for Apalis and Colibri modules

Age	Commit message (Expand)	Author
2015-04-10	MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes	Markos Chandras
2015-02-17	MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions	Markos Chandras
2014-12-11	Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus	Linus Torvalds
2014-11-24	MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration	Ralf Baechle
2014-11-24	MIPS: r4kcache: Add EVA case for protected_writeback_dcache_line	Markos Chandras
2014-06-30	MIPS: KVM: Reformat code and comments	Deng-Cheng Zhu
2014-05-30	MIPS: Add minimal support for OCTEON3 to c-r4k.c	David Daney
2014-05-24	MIPS: MT: Remove SMTC support	Ralf Baechle
2014-03-31	MIPS: Fix gigaton of warning building with microMIPS.	Ralf Baechle
2014-03-26	MIPS: asm: r4kcache: Add EVA cache flushing functions	Leonid Yegoshin
2014-03-26	MIPS: asm: r4kcache: Add protected cache operation for EVA	Leonid Yegoshin
2014-03-26	MIPS: asm: r4kcache: Build flushing code for instruction cache	Leonid Yegoshin
2014-01-15	MIPS: fix blast_icache32 on loongson2	Aaro Koskinen
2014-01-15	MIPS: fix case mismatch in local_r4k_flush_icache_range()	Huacai Chen
2013-10-29	MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.	Ralf Baechle
2013-02-01	MIPS: Whitespace cleanup.	Ralf Baechle
2011-04-06	update David Miller's old email address	Justin P. Mattock
2009-06-17	MIPS: Support 64-byte D-cache line size	Kevin Cernekee
2008-10-11	MIPS: Move headfiles to new location below arch/mips/include	Ralf Baechle