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AgeCommit message (Expand)Author
2018-12-05perf/x86/intel: Add generic branch tracing check to intel_pmu_has_bts()Jiri Olsa
2018-12-05perf/x86/intel: Move branch tracing setup to the Intel-specific source fileJiri Olsa
2018-12-01perf/x86/intel/uncore: Add more IMC PCI IDs for KabyLake and CoffeeLake CPUsKan Liang
2018-11-10perf/x86/intel/uncore: Fix PCI BDF address of M3UPI on SKXKan Liang
2018-10-10perf/x86/intel: Add support/quirk for the MISPREDICT bit on Knights Landing CPUsJacek Tomaka
2018-10-03perf/x86/intel/lbr: Fix incomplete LBR call stackKan Liang
2018-09-05perf/x86/amd/ibs: Don't access non-started eventThomas Gleixner
2018-08-03perf/x86/intel/uncore: Correct fixed counter index check for NHMKan Liang
2018-08-03perf/x86/intel/uncore: Correct fixed counter index check in generic codeKan Liang
2018-05-30perf/x86/intel: Fix event update for auto-reloadKan Liang
2018-05-30perf/x86/intel: Fix large period handling on Broadwell CPUsKan Liang
2018-05-30perf/x86/intel: Properly save/restore the PMU state in the NMI handlerKan Liang
2018-05-30perf/x86/intel: Fix linear IP of PEBS real_ip on Haswell and later CPUsStephane Eranian
2018-05-16perf/x86: Fix possible Spectre-v1 indexing for x86_pmu::event_map()Peter Zijlstra
2018-05-16perf/x86/msr: Fix possible Spectre-v1 indexing in the MSR driverPeter Zijlstra
2018-05-16perf/x86/cstate: Fix possible Spectre-v1 indexing for pkg_msrPeter Zijlstra
2018-05-16perf/x86: Fix possible Spectre-v1 indexing for hw_perf_event cache_*Peter Zijlstra
2018-03-28perf/x86/intel/uncore: Fix multi-domain PCI CHA enumeration bug on Skylake se...Kan Liang
2018-03-28perf/x86/intel: Don't accidentally clear high bits in bdw_limit_period()Dan Carpenter
2018-03-28perf/x86/intel/uncore: Fix Skylake UPI event formatKan Liang
2018-02-25perf/x86: Shut up false-positive -Wmaybe-uninitialized warningArnd Bergmann
2018-02-22x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_steppingJia Zhang
2018-02-13kaiser: fix intel_bts perf crashesHugh Dickins
2018-01-31perf/x86/amd/power: Do not load AMD power module on !AMD platformsXiao Liang
2018-01-05KPTI: Rename to PAGE_TABLE_ISOLATIONKees Cook
2018-01-05kaiser: fix perf crashesHugh Dickins
2017-12-09perf/x86/intel: Account interrupts for PEBS errorsJiri Olsa
2017-08-30perf/x86/intel/rapl: Make package handling more robustThomas Gleixner
2017-08-06perf/x86: Set pmu->module in Intel PMU modulesDavid Carrillo-Cisneros
2017-07-05perf/x86: Reject non sampling events with precise_ipJiri Olsa
2017-07-05perf/x86/intel: Use ULL constant to prevent undefined shift behaviourColin King
2017-07-05perf/x86/intel/uncore: Fix hardcoded socket 0 assumption in the Haswell init ...Prarit Bhargava
2017-07-05perf/x86/intel: Handle exclusive threadid correctly on CPU hotplugZhou Chengming
2017-06-29perf/x86/intel: Add 1G DTLB load/store miss support for SKLKan Liang
2017-05-20perf/x86: Fix Broadwell-EP DRAM RAPL eventsVince Weaver
2017-05-14perf/x86/intel/pt: Add format strings for PTWRITE and power event tracingAlexander Shishkin
2017-04-21perf/x86: Avoid exposing wrong/stale data in intel_pmu_lbr_read_32()Peter Zijlstra
2017-03-22x86/perf: Fix CR4.PCE propagation to use active_mm instead of mmAndy Lutomirski
2017-02-09perf/x86/intel/uncore: Clean up hotplug conversion falloutThomas Gleixner
2017-01-09perf/x86/intel/cstate: Prevent hotplug callback leakThomas Gleixner
2017-01-09perf/x86: Fix exclusion of BTS and LBR for GoldmontAndi Kleen
2016-12-06perf/x86: Fix full width counter, counter overflowPeter Zijlstra (Intel)
2016-12-06perf/x86/intel: Enable C-state residency events for Knights MillPiotr Luc
2016-11-22perf/x86/intel/uncore: Allow only a single PMU/box within an events groupPeter Zijlstra
2016-11-22perf/x86/intel: Cure bogus unwind from PEBS entriesPeter Zijlstra
2016-11-22perf/x86: Restore TASK_SIZE check on frame pointerJohannes Weiner
2016-11-18perf/x86: Add perf support for AMD family-17h processorsJanakarajan Natarajan
2016-11-16perf/x86/uncore: Fix crash by removing bogus event_list[] handling for SNB cl...Kan Liang
2016-11-11perf/x86/intel/uncore: Add more Intel uncore IMC PCI IDs for SkyLakeKan Liang
2016-10-28perf/x86/intel: Honour the CPUID for number of fixed counters in hypervisorsImre Palik
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