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At host 1 code, we should use UH1_XXXX. The wrong register
access causing a bug that the u-disk disconnion at host 1
can't be recognized after system resume.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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At mx6, if usb wakeup is not enabled, the PHY's power
will be off during the system suspend, so the dp/dm
will be unknown after the system resumes, it may wake up
controller at some boards since dp/dm's status satisfies
wake up condition. If the controller is waken up, the
PHCD will be cleared automatically.
According to IC requirement, after PHCD is cleared, we
need to wait 1ms before clear PHY's clock gate to wait
PHY's clock stable. At above condition, the PHCD is cleared
automatically, it may less than 1ms before we clear
PHY's clock gate, then, software operation to clear PHY's
clock gate will be useless. At this case, the PHY will works
abnormal, and cause the controller hang when we write some registers
(eg, portsc).
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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the ARM core version we are using on the i.MX6 is
r2p10, thus, we need apply this ARM errata
Signed-off-by: Jason Liu <r64343@freescale.com>
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The PL310 version we are using on the i.MX6Q/DL is r3p1-50rel0,
thus, we need enable this errata for i.MX6DQ/DL/SOLO.
i.MX6SL has the PL310 version: r3p2, no need enable this errata.
Signed-off-by: Jason Liu <r64343@freescale.com>
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arm: Add ARM ERRATA 775420 workaround
Workaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0) erratum.
In case a date cache maintenance operation aborts with MMU exception, it
might cause the processor to deadlock. This workaround puts DSB before
executing ISB if an abort may occur on cache maintenance.
Based on work by Kouei Abe and feedback from Catalin Marinas.
Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
[ horms@verge.net.au: Changed to implementation
suggested by catalin.marinas@arm.com ]
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The display MIX can be power gated when EPDC, PXP and LCDIF are all inactive.
This will save around 1.5mW-1.8mW of power in system IDLE mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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For imx6 serial silicon, fec MDC clock parent is ipg 66MHz.
The current clock file define the clock source is enet_pll8 50Mhz.
So, the MDC clock is more than 2.5Mhz after divider.
The phy Ar8031 work fine in current MDC clock, which shows the phy
have exceeding flexibility. Correct the parent clock source to make
MDC clock little than 2.5Mhz.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add a command line option to route the ENET interrupts to the GPIO_1_6.
To route the ENET interrupts to GPIO_6 add "enet_gpio_6" to the
kernel command line.
Also remove the CONFIG option (MX6_ENET_IRQ_TO_GPIO).
This commit should be applied on top of following commits:
72c86f0b9a953e91bb1ed31021b71f337050bc28
808863866d2c17aeb3e70a7fcd094bd96db4b601
bae4d40849f3acdd9663f5a0857c9415ed7e6d5d
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add chip revision checking and only enable DISPLAY power gating on TO1.2
Signed-off-by: Robby Cai <R63905@freescale.com>
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The commit 0c0334779a08cca6c5a509570c944fe229837a21
corrected the v_period/v_wait_cnt, h_period/h_wait_cnt caculation in elcdif
framebuffer driver but in WVGA panel timing setting the left_margin and
upper_margin includes the length of hsyn_len and vsyn_len.
Thus the timing setting for lcd panel is not correct.
This patch fixes it.
Signed-off-by: Robby Cai <R63905@freescale.com>
(cherry picked from commit 9c04adb3c7b95459153873556ff0566d837ee325)
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Set bit18 of gpr1 before enter into supend, and clean it
after resume, can fix the following errata.
Errata ERR005723_PCIe PCIe does not support L2 Power Down.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Add VPU_IOC_LOCK_DEV to lock VPU device
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
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Correct @file comment in mxc_vpu.h
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
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Add missing parenthesis
Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>
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There is single method to set clock-rate for both audio and video pll-s
in i.MX6q clock system implementation. That's possible due to they have
similar set of registers with a different bases. But there is also one
common register: CCM_ANALOG_MISC2, which contains post-dividers.
In current implementation, independently of whether audio or video clock
is going to be set, the mask 0xc0000000 is applied to MISC2 register.
This means, that if the audio clock rate is changed, the video clock
post-dividers possibly will be corrupted.
This patch fixes the issue described above.
Signed-off-by: Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>
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CCM state machine has restriction that, everytime enable
LPM mode, we need to make sure last wakeup from LPM mode
is a dsm_wakeup_signal, which means the wakeup source
must be seen by GPC, then CCM will clean its state machine
and re-sample necessary signal to decide whether it can
enter LPM mode. Here we use the forever pending irq #125,
unmask it before we enable LPM mode and mask it after LPM
is enabled, this flow will make sure CCM state machine in
reliable state before we enter LPM mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
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We need to pay attention to writing the 'CCM Serial Clock Multiplexer
Register 1' register since the write value/divider map and the read
value/divider for aclk_podf field are different. In order to keep
the divider value unchanged when writing the other fields of the
register, we need to fixup the write value.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Minor correction that broke build - 2 lines were swapped.
Signed-off-by: Jay Monkman <jay.monkman@freescale.com>
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The read/write values of aclk_podf[20:22] field in register 'CCM Serial
Clock Multiplexer Register 1' do not match with each other. The read/
write/divider values have the relationship described by the following
table:
============================================================
write value read value description
3b'000 3b'110 divided by 7
3b'001 3b'111 divided by 8
3b'010 3b'100 divided by 5
3b'011 3b'101 divided by 6
3b'100 3b'010 divided by 3
3b'101 3b'011 divided by 4
3b'110 3b'000 divided by 1
3b'111 3b'001 divided by 2(default)
============================================================
This patch corrects the emi_clk set/get rate functions according to
the above table. On i.MX6Q, emi_clk is used by MIPI CSI2 module as
ccm_pixel_clk, while on i.MX6SDL, it is not used by any module.
The patch may resolve the 1080P30 MIPI camera preview blur issue
indirectly by increasing ccm_pixel_clk for i.MX6Q.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Minor correction that broke build.
Signed-off-by: Jay Monkman <jay.monkman@freescale.com>
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Add HDCP IOCTL command define
Signed-off-by: Sandor <R01008@freescale.com>
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Adjust MX6 SabreSD board HDMI PHY configuration
to pass HDMI CTS.
Signed-off-by: Sandor <R01008@freescale.com>
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There is no need to enable warm reset of SRC_SCR
register when we only need to do a VPU reset.
Signed-off-by: Anson Huang <b20788@freescale.com>
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MX6DQ/DL SabreSD board HDMI compliance test 7-15 failed, because VCEC2 is
0.276V, but the HDMI compliance test specification 1.4a requried
the VCEC2 should in the range 0.196V to 0.274V.
Remove R657(47K pull up resistance) in SabreSD board and setting
KEY_ROW2_HDMI_TX_CEC pin internal pull up to 100K, the VCEC2 is 0.245V,
pass 7-15 test.
Signed-off-by: Sandor <R01008@freescale.com>
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1. eim_clk's divider is bit[22:20], when read from this register,
the value of bit22 and bit21 are the opposite value of actual
value, so we need to handle it in clk get rate function of eim_clk.
2. For VPU running at 352M case on i.MX6Q, we need to set eim
clk to 176M, as its parent's freq is 352M. Otherwise, it is set
to 198M.
Signed-off-by: Anson Huang <b20788@freescale.com>
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0x0110_0000 ~ 0x01EF_FFFF 14MB would be used for MEM allocation.
But the "IORESOURCE_SIZEALIGN" would be used during the Linux PCI/PCIe
subsystem probe/scan the bus and allocate the resources.
If the 8MB MEM is required, the start address 0x0180_0000 would be used
by Linux PCI/PCIe subsystem, trying to allocate the 8MB MEM space
(0x0180_0000 ~ 0x01FF_FFFF), this operation would be failed.
Because the address if outof 0x0110_0000 ~ 0x01EF_FFFF limitaion.
solution:
One method to allocate the 8MB(the biggest size of IO/MEM space) MEM
space on iMX6 PCIe RC.
Adjust the layout of the 16MB address space of iMX6 PCIe RC, like this:
* RC:
* 0x0100_0000 --- 0x01DF_FFFF 14MB IORESOURCE_MEM
* 0x01E0_0000 --- 0x01EF_FFFF 1MB IORESOURCE_IO
* 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + MSI + Registers
The 8MB space would be allocated from 0x0100_0000 ~ 0x017F_FFFF.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Correct the definitions of ANADIG_ANA_MISC2_REG0_STEP_TIME_MASK and
ANADIG_ANA_MISC2_REG2_STEP_TIME_MASK to 0x03000000 and 0x30000000 respectively
Signed-off-by: Peter Chan <B18700@freescale.com>
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ID wakeup interrupt is only needed at OTG config.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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The static variables needs to be initialized at init function,
or the value may be incorrect during the module load/unload process.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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1. The ipg_per clock rate setting should be done after
its parent initilization done, otherwise it will get wrong
parent rate and lead to incorrect rate setting;
2. The parent info of emi_clk has been changed in latest RM,
need to update it according to RM, the parent info is as below:
2b'00: 396M PFD;
2b'01: PLL3;
2b'10: AXI;
2b'11: 352M PFD.
Signed-off-by: Anson Huang <b20788@freescale.com>
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sdma: bd is bufferable dma buffer, interrupt handler can not get correct
data after sdma script updated. Which will cause there is no interrupt
after failed period number times in the interrupt handler.
This is a workaround.
Signed-off-by: b02247 <b02247@freescale.com>
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Applied patch from customer to prevent DMA memory
fragmentation. Customer reported system crashes due to running out of
DMA-able memory while playing videos. Reported in CT42391649.
Signed-off-by: Jay Monkman <jay.monkman@freescale.com>
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imx6dq have 3 i2c controllers and 5 ecspi,imx6dl have 4 i2c4
controllers and 4 ecspi. imx6dl i2c4 clock source is routed
from pll3 through to ecspi_root gate.
Add i2c4 bus support for sabresd/auto, and arm2 platforms.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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The following commit:
6f394da8b374dc4a063209deedeb5d8a62ae4c74
introduced a bug that does not enable audio PLL when its
frequency is something other than 24MHz.
This patch ensures that Audio PLL will be enabled for
all frequencies.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The code reads the direction register and returns value from the
DR register if pin is configured as output and from the PSR
register if pin is configured as input.
Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>
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The callers of ipu_enable_irq() may choose to enable a sync interrupt
without calling ipu_request_irq() to assign an interrupt handler to
that interrupt beforehand. This is wrong and may cause NULL interrupt
handler being called in the IPU sync interrupt handler and finally
makes the system hang. This patch changes the return type of the
function ipu_enable_irq() from 'void' to 'int' so that the callers
may be aware of the error.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Store SDMA channel and buffer descriptors in IRAM for MX6SL.
This will improve the audio playback power when both the
SDMA and audio buffers are all in IRAM. The DDR will be
self-refresh for longer periods of time.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Move MMDC to be sourced from PLL2_200M in audio mode.
Set the DDR freq to be 100MHz in audio mode.
Add code to drop DDR to 25MHz when ARM is in WFI while
playing audio. This will be the case when SDMA is transferring
data from the audio buffer in IRAM. Also float the DDR IO
pins in this state.
Set Audio PLL to bypass mode.
Source both WM8962 and SSI2 from audio PLL (PLL4).
Set AHB to 8MHz in Audio playback mode when ARM is going to enter WFI.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The DDR freq change code and the low power WFI code in
MX6SL runs from non-cacheable but bufferable IRAM space.
Its possible for an eviction to occur from the L1
and/or L2 sync buffers after the DDR has been put into
self-refresh. This will cause the system to hang. To
avoid this ensure that the L1/L2 sync buffers are drained
properly.
Following is the info from ARM on L2 store buffers:
**********************************************************
You can use L2 sync operation to drain L2store buffer manually,
and the store buffer would be drained in such conditions:
* store buffer slot is immediately drained if targeting
device memory area
* store buffer slots are drained as soon as they are full
* store buffer is drained at each strongly ordered read
occurrence in slave ports
* store buffer is drained at each strongly ordered write
occurrence in slave ports
* as soon as all three slots of the store buffer contain data,
the least recently accessed slot starts draining
* if a hazard is detected in a store buffer slot , that slot
is drained to resolve the hazard
* store buffer slots are drained when a lock ed transaction is
received by one slave port
* store buffer slots are drained when a transaction targeting
the configuration registers is received by one slave port
* store buffer slots are automatically drained after 256 cycles
of presence in the store buffer.
You can refer to 2.5.3 Store buffer operation of PL310 trm(r3p3, DDI0246H)
for the detail.
You have to apply the explicit cache sync operation, which should be
followed by DSB, before entering the low power mode. And the bit0 of
the cache sync register(base offset 0x730) should be polling to guarantee
that the PL310 has finished sync operation.
PL310 owns three 256 bit entry store buffer & eviction buffer, and
four 256 bit LFB & LRB, and Cache sync would complete when all buffers,
LRB, LFB, STB, and EB, are empty.
The actual overhead should be close to your L3 access latency.
*************************************************************************
~
~
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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- For id/vbus value from otgsc, it needs 1ms debounce time
after the PHY enters stable.
- Delete the useless code.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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- Replace portsc to otgsc
- Add define for otgsc
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Add HDMI CEC IOMUX setting for MX6DL SabreSD board.
Signed-off-by: Sandor <R01008@freescale.com>
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Add HDMI CEC PAD setting for MX6DL.
Signed-off-by: Sandor <R01008@freescale.com>
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The clock, output from wm8962's FLL, is sometimes inaccurate.
This's because 26MHz is not quite stable for wm8962's internal FLL,
So change to 24MHz, the value recommended by Wolfson,
which has been used on SabreSD for quite a long time.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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Move clock disable from MSL to driver
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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We have wrong understanding that reset controller will put PHY
to be out of low power automatically, but in fact, it is not.
So, we should put PHY to be out of low power explicitly if the
portsc.phcd = 1 before we need to access controller's register.
Some register writing will hang system (eg,PERIODICLISTBASE),
some reading will not get the correct value (eg, otgsc).
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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In order to fix the performance issue on ENET when WAIT mode
is activated, route the ENET interrupts to a GPIO on all MX6DL boards.
This patch must be applied on top of:
MX6Q/DL-Fix Ethernet performance issue when WAIT mode is active
808863866d2c17aeb3e70a7fcd094bd96db4b601
bae4d40849f3acdd9663f5a0857c9415ed7e6d5d
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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According to hardware design requirement, the WAIT mode setting bit17
need to be set if system enter suspend without ARM power gated, so in
standby mode, we can NOT clear this bit.
Signed-off-by: Anson Huang <b20788@freescale.com>
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All of the interrupts from the ENET block are not routed to
the GPC block. Hence ENET interrupts are not able to wake
up the SOC when the system is in WAIT mode. And the ENET
interrupt gets serviced only when another interrupt causes
the SOC to exit WAIT mode. This impacts the ENET performance.
To fix the issue two options:
1. Route the ENET interrupt to a GPIO. Need to enable the
CONFIG_MX6_ENET_IRQ_TO_GPIO in the config.
This patch provides support for routing the ENET interrupt
to GPIO_1_6. Routing to this GPIO requires no HW board mods.
If the GPIO_1_6 is being used for some other peripheral,
this patch can be followed to route the ENET interrupt to
any other GPIO though a HW mode maybe required.
2. If the GPIO mechanism cannot be used and is not enabled
by the above mentioned config, the patch will disable entry
to WAIT mode until ENET clock is active. When the ENET clock
is disabled, WAIT mode will be automatically enetered.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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For MLB uses iram for data transfer, and there's a missing of dependency
on iram in MLB's clock setting, MLB can't receive data in wait mode.
We need to add ocram clock dependency in MLB clock.
Signed-off-by: Terry Lv <r65388@freescale.com>
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