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Change 996M setpoint voltage according to datasheet,
lower VDDARM_CAP from 1.275V to 1.25V, and VDDSOC/PU_CAP
from 1.275V to 1.175V.
Signed-off-by: Anson Huang <b20788@freescale.com>
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remove the wake up flag for VOL_DOWN and VOL_UP keys for sabresd B4 and
above board.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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We must set the DMA mask for esdhc device.
To avoid the following crash when we do not have highmem pages:
[<c0044f90>] (__dabt_svc+0x70/0xa0) from [<c00cf460>]
[<c00cf460>] (mempool_alloc+0x3c/0x108) from [<c00f4aa4>]
[<c00f4aa4>] (blk_queue_bounce+0xc0/0x2fc) from [<c023761c>]
[<c023761c>] (__make_request+0x20/0x2b8) from [<c0235bb4>]
[<c0235bb4>] (generic_make_request+0x3b4/0x4cc) from [<c0235d74>]
[<c0235d74>] (submit_bio+0xa8/0x128) from [<c01279c4>]
[<c01279c4>] (submit_bh+0x108/0x178) from [<c012baa0>]
[<c012baa0>] (block_read_full_pag+e0x278/0x394) from [<c00cd520>]
[<c00cd520>] (do_read_cache_page+0x70/0x154) from [<c00cd64c>]
[<c00cd64c>] (read_cache_page_async+0x1c/0x24) from [<c00cd65c>]
[<c00cd65c>] (read_cache_page+0x8/0x10) from [<c014c354>]
[<c014c354>] (read_dev_sector+0x30/0x68) from [<c014dd4c>]
[<c014dd4c>] (read_lba+0xa0/0x164) from [<c014e300>]
[<c014e300>] (efi_partition+0x9c/0xed4) from [<c014ca0c>]
[<c014ca0c>] (rescan_partitions+0x15c/0x480) from [<c012f190>]
[<c012f190>] (__blkdev_get+0x324/0x394) from [<c012f300>]
[<c012f300>] (blkdev_get+0x100/0x358) from [<c023e5f4>]
[<c023e5f4>] (register_disk+0x140/0x164) from [<c023e73c>]
[<c023e73c>] (add_disk+0x124/0x2a0) from [<c03a7528>]
[<c03a7528>] (mmc_add_disk+0x10/0x68) from [<c03a7820>]
[<c03a7820>] (mmc_blk_probe+0x15c/0x20c) from [<c039cc90>]
[<c039cc90>] (mmc_bus_probe+0x18/0x1c) from [<c0294e28>]
When our DDR size is small or reserved memory are large and
the lowmem can cover all the available pages for kernel,
the highmem pages will not be setup. That means the page_pool
for bounce queue can not be create in init_emergency_pool().
And page_pool will stay NULL without initialized.
In the mmc/card/queue.c the blk_queue_bounce_limit()
function will be called in mmc_init_queue() to
initialize the request_queue and it's bounce_gfp.
If we do not define the DMA mask for our platform,
then the BLK_BOUNCE_HIGH (lowmem pfn) will be set
as limit to queue bounce, which means the blk_queue_bounce
will use page_pool to iterate over the bio segment.
Under the circumstances that highmem is not setup,
the page_pool is null, and causes kernel crash.
After set the DMA mask for esdhci device, the page_pool
will not be used to iterate over the bio segment.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Previous setting of PUPSCR is 0x202, which means there is only ~63us
for LDO ramp up, sometimes, system fail to resume by USB remote wake up,
increase this timing to fix USB remote wake up issue.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Conflicts:
drivers/mxc/vpu/mxc_vpu.c
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We must set the DMA mask for esdhc device.
To avoid the following crash when we do not have highmem pages:
[<c0044f90>] (__dabt_svc+0x70/0xa0) from [<c00cf460>]
[<c00cf460>] (mempool_alloc+0x3c/0x108) from [<c00f4aa4>]
[<c00f4aa4>] (blk_queue_bounce+0xc0/0x2fc) from [<c023761c>]
[<c023761c>] (__make_request+0x20/0x2b8) from [<c0235bb4>
[<c0235bb4>] (generic_make_request+0x3b4/0x4cc) from [<c0235d74>]
[<c0235d74>] (submit_bio+0xa8/0x128) from [<c01279c4>]
[<c01279c4>] (submit_bh+0x108/0x178) from [<c012baa0>]
[<c012baa0>] (block_read_full_pag+e0x278/0x394) from [<c00cd520>]
[<c00cd520>] (do_read_cache_page+0x70/0x154) from [<c00cd64c>]
[<c00cd64c>] (read_cache_page_async+0x1c/0x24) from [<c00cd65c>]
[<c00cd65c>] (read_cache_page+0x8/0x10) from [<c014c354>]
[<c014c354>] (read_dev_sector+0x30/0x68) from [<c014dd4c>]
[<c014dd4c>] (read_lba+0xa0/0x164) from [<c014e300>]
[<c014e300>] (efi_partition+0x9c/0xed4) from [<c014ca0c>]
[<c014ca0c>] (rescan_partitions+0x15c/0x480) from [<c012f190>]
[<c012f190>] (__blkdev_get+0x324/0x394) from [<c012f300>]
[<c012f300>] (blkdev_get+0x100/0x358) from [<c023e5f4>]
[<c023e5f4>] (register_disk+0x140/0x164) from [<c023e73c>]
[<c023e73c>] (add_disk+0x124/0x2a0) from [<c03a7528>]
[<c03a7528>] (mmc_add_disk+0x10/0x68) from [<c03a7820>]
[<c03a7820>] (mmc_blk_probe+0x15c/0x20c) from [<c039cc90>]
[<c039cc90>] (mmc_bus_probe+0x18/0x1c) from [<c0294e28>]
When our DDR size is small or reserved memory are large and
the lowmem can cover all the available pages for kernel,
the highmem pages will not be setup. That means the page_pool
for bounce queue can not be create in init_emergency_pool().
And page_pool will stay NULL without initialized.
In the mmc/card/queue.c the blk_queue_bounce_limit()
function will be called in mmc_init_queue() to
initialize the request_queue and it's bounce_gfp.
If we do not define the DMA mask for our platform,
then the BLK_BOUNCE_HIGH (lowmem pfn) will be set
as limit to queue bounce, which means the blk_queue_bounce
will use page_pool to iterate over the bio segment.
Under the circumstances that highmem is not setup,
the page_pool is null, and causes kernel crash.
After set the DMA mask for esdhci device, the page_pool
will not be used to iterate over the bio segment.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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1. Revert ENGR00231910 Do not disable PU regulator,revert the PU
regulator patch;
2. VPU reset register address is different on MX6 and MX5. It can
fix ENGR00230203 [Android_MX6DL_SD] Gallery: System hang after resume
from suspend during video playback. 20%
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
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If system enter suspend/resume during VPU encoding on Rigel, there will be
"VPU blocking: timeout." error . But there is ok if enter suspend/resume
during VPU decoding and enter suspend/resume during encoding/decoding on
Arik, until now we didn't know the root cause, so revert it firstly.
Because the previous patch about PU regulator is composed with four commits
and hard to revert, now we adopt simplest way that do not disable PU regulator
in low level. The negative impact is there will several mA increasment in
suspend, we will fix it ASAP.
Signed-off-by: Robin Gong <b38343@freescale.com>
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SD card card detection and NFC controller CS2 share
the same pin on ARD platform. However CS2 is not
connected to the socket. This signal was removed
from the sabreauto board file.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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not set wm8958 codec as builtin in imx6_defconfig
Signed-off-by: Gary Zhang <b13634@freescale.com>
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There is 6% tolerance for PFM momde in standby so we need set 0.975V(>0.9V+%6)
for VDDSOC and VDDARM which maybe impact system resume ability.
Another two change is:
1.set VDDARM and VDDSOC standby voltage by setting PFUZE register directly,it
is not very friendly.So use more common "state_mem" in constrain of regulator
to set standby voltage.
2.align sabreauto code with sabresd
Signed-off-by: Robin Gong <b38343@freescale.com>
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In mx6q arm2 board, the gpmi conflicts with SD module.
But the defconfig has enabled the gpmi by default.
So we have to add a kernel cmdline to enable the gpmi by hand in arm2 board.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Add scaling_available_freqs attribute in cpufreq for i.MX
can get cpufreq table info with:
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
996000 792000 396000
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Add scaling_available_freqs attribute in cpufreq for i.MX
can get cpufreq table info with:
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
996000 792000 396000
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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SDP boards layout have board's width aligne with LVDS's height
Update the mma8451 and mag3110's config to algin with SDP board
Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
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The USB FS eye test will fail in MX6 board if the 3V USB phy LDO is not enabled.
Setting enable bit (bit-0) of LDO 3p0 will make 3p0 LDO to use bandgap output as
reference voltage, LDO output will be accurate. And HW team suggest that it is
better to raise the voltage of USB 3p0 phy LDO 3.2V to pass the USB compliance
testing.
- Implement vdd3p0 regulator enable and disable function to support
enable and disable the LDO 3p0 regulator.
- Use regulator API to enable the USB 3p0 phy LDO and raise the LDO
to 3.2V during system boot up. And disable the LDO before system
enter suspend and enable the LDO again after system resume.
Signed-off-by: make shi <b15407@freescale.com>
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imx_3.0.35_android_r13.4.y
Conflicts:
arch/arm/configs/imx6s_updater_defconfig
arch/arm/include/asm/hardware/coresight.h
arch/arm/kernel/etm.c
arch/arm/mach-mx6/board-mx6q_sabresd.c
arch/arm/mach-mx6/cpu_op-mx6.c
arch/arm/mach-mx6/mx6_suspend.S
arch/arm/mach-mx6/mx6sl_wfi.S
arch/arm/mach-mx6/pm.c
arch/arm/mach-mx6/system.c
arch/arm/plat-mxc/cpufreq.c
drivers/media/video/mxc/capture/ov5640_mipi.c
drivers/mfd/mxc-hdmi-core.c
drivers/mmc/host/sdhci.c
drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c
drivers/power/sabresd_battery.c
drivers/video/mxc/mxc_ipuv3_fb.c
include/linux/mfd/mxc-hdmi-core.h
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Only enable power gating for PXP and EPDC. The feature for ELCDIF still need to
be verified.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Enable CONFIG_VIDEO_MXC_PXP_V4L2 option.
Signed-off-by: Robby Cai <R63905@freescale.com>
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* Add ad7280 I2C device support
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Oscar Luna <r01160@freescale.com>
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Add eCompass support on Sabreauto platform
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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Configuration file modified to support NAND flash, SPI-NOR,
WEIM NOR and SD card on the same image.
Bootloader arguments will be used to choose between them.
Arguments on uboot are:
spi-nor
weim-nor
By default NAND is configured if neither spi-nor or weim-nor are used
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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* Adv7180 use tvin io_init callback to configure csi0/ipu
mux settings mx6q_csi0_io_init.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Write to the MMDC registers when resetting the MMDC after the
DDR I/Os have been floated.
This fixes the bug introduced by the commit:
"2a2f65bd07ad0f947794c2e5f2f825121805d663
MX6SL-Reset MMDC read FIFO in low power IDLE"
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The REG_BYPASS_COUNTER(RBC) holds off interrupts when the PGC
block is sending signals to power gate the core. This is apart
from the RBC counter's basic functionality to act as counter to
power down the analog portions of the chip.
But the counter needs to be set/cleared only when no interrupts
are pending. And also for correct hold off the interrupts, enable the
counter as close to WFI as possible.
The RBC counts CKIL cycles (32KHz)
So follow the following steps to set the counter
in suspend/resume in mx6_suspend.S:
1. Mask all the GPC interrupts.
2. Write the counter value to the RBC
3. Enable the RBC
4. Unmask all the interrupts.
5. Busy wait for a few usecs to wait for RBC to start counting
in case an interrupt is pending.
4. Execute WFI
Reset the counter after resume in pm.c:
1. Mask all the GPC interrupts.
2. Disable the counter.
3. Set the RBC counter to 0.
4. Wait for 80usec for the write to get accepted.
5. Unmask all the interrupts.
With the above steps, we can minimize the PDNSCR and PUPSCR counters
in the GPC. The basic condition for the RBC counter:
RBC count >= 25 * IPG_CLK + PDNSCR_SW2ISO.
PDNSCR_SW2ISO = PDNSCR_ISO = 1 (counts in IPG_CLK)
PUPSCR_SW2ISO = PUPSCR_ISO = 2 (counts in 32K)
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix all build warnings in files:
arch/arm/mach-mx6/board-mx6sl_common.h
arch/arm/mach-mx6/board-mx6sl_evk.c
arch/arm/mach-mx6/clock_mx6sl.c
arch/arm/mach-mx6/cpu_regulator-mx6.c
arch/arm/mach-mx6/pm.c
arch/arm/mach-mx6/system.c
arch/arm/plat-mxc/dvfs_core.c
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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MMDC can clock in bad data due to the glitches caused by
changing the setting of various DDR IO pads in low power
IDLE to save power. Solution is to reset the MMDC read FIFO
before the DDR exits self-refresh.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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If "debug_uart" is specified in the command line, uart will
be sourced from 24MHz XTAL. This is required for getting the
correct power measurements on MX6SL.
Certain analog power optimizations are done only if ALL PLLs
are bypassed on MX6SL. To verify this path, we need to ensure
that UART is not sourced from PLL3.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Update the VDDARM and VDDSOC voltages based on IMX6SLCEC_Rev0
datasheet.
As the voltages for ARM @ 198MHz and ARM @ 396MHz are the same
remove the 198MHz working point.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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1. Fix AHB clock not changed to 3MHz in IDLE mode
2. Fix system hangs in IDLE mode due to changes made for LOCKDEP
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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1. Fix mutex_lock nested issue in idle mode
2. Fix mutex_lock nested issue in suspend mode
3. Fix spin_lock nested issue in busfreq
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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This patch support primary framebuffer(fb0) late init and ipu1
bypass reset if the user needs smooth UI transition feature from
bootloader to system UI. The user needs to add 'fb0base=' and
'fbmem=' options to kernel command line to enable the feature.
This patch is for Android kernel only.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 4e01f875fb3623cf70a9ae7949d9a8aac5b5a21e)
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This patch removes linux boot logo support so that bootloader
splashimage content may be kept after booting into kernel stage.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 567ad8dc9a9a923b8ebdc6379904fc0030e2bb06)
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This patch adds CONFIG_MX6_CLK_FOR_BOOTUI_TRANS support for mx6_
android_defconfig file.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit a768c2f2a4ddfb2091b7cb541a4c5b218f6a48d9)
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This patch enables PWM1 clock for MX6 sabresd platform if CONFIG_MX6_
CLK_FOR_BOOTUI_TRANS is set, which may keep the backlight being on
since bootloader stage and the user may see the display content without
backlight blanking. This patch is for Android kernel only.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit db28f2ad17906617ba1c12e2a2512a819ad389cb)
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This patch enables IPU1 related clocks by default if CONFIG_
MX6_CLK_FOR_BOOTUI_TRANS is set, to support smooth UI tran-
sition from bootloader to kernel and keeps the specific trees
(told in below) unchanged. The kernel assumes that the boot-
loader uses IPU1 DI1 and LDB DI1 to driver a LVDS display
panel to do splashimage. LDB should works in separate mode
or single mode. The IPU1 related clock trees are:
1) MX6DQ SabreSD:
ipu1_clk --
osc_clk(24M)->pll2_528_bus_main_clk(528M)->periph_clk(528M)
->mmdc_ch0_axi_clk(528M)->ipu1_clk(264M)
ipu1_pixel_clk_1 --
osc_clk(24M)->pll2_528_bus_main_clk(528M)->
pll2_pfd_352M(452.57M)->ldb_di1_clk(64.65M)->
ipu1_di_clk_1(64.65M)->ipu1_pixel_clk_1(64.65M)
2) MX6DL SabreSD:
ipu1_clk --
osc_clk(24M)->pll3_usb_otg_main_clk(480M)->
pll3_pfd_540M(540M)->ipu1_clk(270M)
ipu1_pixel_clk_1 --
osc_clk(24M)->pll2_528_bus_main_clk(528M)->
pll2_pfd_352M(452.57M)->ldb_di1_clk(64.65M)->
ipu1_di_clk_1(64.65M)->ipu1_pixel_clk_1(64.65M)
So for MX6DQ and MX6DL, with CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
set, this patch keeps ipu1_clk, ldb_di1_clk, ipu1_di_clk_1 and
pll2_pfd_352M being enabled and keeps ipu1_di_clk_1's parent
unchanged. And, for MX6DL, with CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
set this patch keeps pll3_usb_otg_main_clk and pll3_pfd_540M
being enabled. This patch is for Android kernel only.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit fea14a67c254e428fc241a3f3165a3ec9f814076)
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This patch adds CONFIG_MX6_CLK_FOR_BOOTUI_TRANS support. Setting
this Kconfig may keep enable IPU related clocks and PWM clocks
and avoid setting IPU related clocks' parents when initializing
clock tree so that bootloader splashimage can transition to
kernel smoothly.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 21b5e4d436666967585313948a03421da1f8f68b)
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This patch changes to connect LDB with IPU1 instead of IPU2 and
connect HDMI with IPU2 instead of IPU1. This is to align with
uboot splashimage setting, as LDB is connected with IPU1 in uboot
to drive display. In this way, we may keep the display channel
running from uboot to kernel until users re-initialize the fb.
This patch is for Android kernel only.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 264155b49eba9093d1ebad0d3e265417553a3d38)
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This patch supports to reserve primary framebuffer's memory
separately if its base address is set in kernel command line
with 'fb0base=' option. To support this feature, note that
'fbmem=' is also required to be set to specify the size of the
memory reserved for the primary framebuffer. This patch is for
Android kernel only.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 9bcc99c5e775c774d2092690a37e4c20e338e570)
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As there is only one IPU embedded in MX6DL and two IPUs embedded
in MX6DQ. The max ipuv3 fb platform driver number is two for
MX6DL and four for MX6DQ.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit c0fef04f59f9baaa03b182fb0fc1597df1a466be)
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This patch initializes late init field to false for IPUv3 fb pdata,
so we don't support late init by default unless we change them to
true in other places specificly.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit cc9baf8aa84f4dd0120aa85960d254646a3aa523)
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This patch initializes bypass reset field to false for IPUv3 pdata,
so we don't support bypass reset by default unless we change them
to true in other places specificly.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 6c294588a1987810ed4d45bcb5e1d3416d66d0be)
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This patch adds late init field support in ipuv3 fb
platform data, so that a platform may choose to not
to initialize framebuffer until the user triggers
set_par(), which may support smooth transition from
bootloader splashimage to system UI.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 3a2547ac167fb2c06d9f63c7a925b9ebdc896d96)
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This patch adds bypass reset field support in ipuv3
platform data, so that a platform may choose not to
reset ipuv3 when doing probe, which may support
smooth transition from bootloader splashimage to
system UI.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit e558b2b6877a2b230c564a1c621bbba3d546f5f7)
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Add gpumem=<size>M kernel parameter for user
to specify the size of reserved memory for GPU driver.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Add csi v4l2 platform device only when 'csi' is assigned in cmdline.
Because there's pin conflicts between csi and epdc.
Signed-off-by: Robby Cai <R63905@freescale.com>
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For DQ and DL, we must make sure DDR can be accessed after resume,
our code did NOT get a valid base address for MMDC to exit from
DVFS mode, need to fix it.
According to ARM, we only need to save r0-r3 and r12 before calling
C function.
Signed-off-by: Anson Huang <b20788@freescale.com>
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issue:
Once entering low power idle mode, pll2_400 will be bypass which will change
the clk rate of sdhc root clk. so far, there's no mechanism to inform sdhc
for changing of root clk in current driver structure.
fix:
Revert "ENGR00226096 mx6sl: remove high set point for usdhc"
This reverts commit 97aee96a34ca63da0d1d602a19b3a444352e5803.
Acked-by: Robby CAI <r63905@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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Setup uart2 to enable bluetooth basic functionality on mx6sl evk board.
DMA mode was not enabled for uart2 operation.
Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
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