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since pll1 have a limit that cannot scaling down to 650M and below
so change the 600M WP to 672MHz.
otherwise, the 600WP's clock will depens on last frequency.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Added the new 1.2GHz working point.
Currently 'arm_freq=1200" should be added to commandline
for the core to run at 1.2GHz. Also ensure that the appropriate
HW board mods have been done to set VDDARM_IN at 1.425V.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The LVDS display direction should be aligned with camera sensor.
So we rotate it with 180 degree.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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enable ipv6 Privacy Extension,or netd commandlistener will
report "cann't find /proc/sys/net/ipv6/conf/wlan0/use_tempaddr".
Signed-off-by: Zhou Jianzheng <B38613@freescale.com>
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Add license header to android.h
Fix the copyright to devices.c
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Due to the wait mode implementation in current BSP is not compatible
with cpu hotplug, so disable the hotplug operations when system entry in
earlysyspend mode.
Will re-enabled it if wait mode issue is fixed
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Fix a typo when adding 600M WP, the voltage value is wrong,
it will lead a warnning when change to this WP:
COULD NOT SET GP VOLTAGE!!!!
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add USB_ACM config for Android kernel
Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
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Previous PLL1 freq change is done by switching CPU clock
to 400M pfd or 24M OSC, then modifying
PLL1 div directly, and switch back CPU clock immediately,
it will result in CPU clock stop during PLL1 hardware lock
period, thus, DRAM FIFO may blocked by the data CPU
requested before PLL1 clock changed, and it will block other devices
accessing DRAM, such as IPU, VPU etc. It will cause
underrun or hang issue. We should wait PLL1 lock, then switch
back.
Signed-off-by: Anson Huang <b20788@freescale.com>
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As mx6q soc use one clock to provide for cpu and local timer,
the local timers will be stopped when enter wait mode.
This causes system hang when enter wait mode with local timer
enabled. So we should switch the clock event to GPT
broadcast clock event before entering wait mode, and disable
local timers. Todo this, following changes made:
* In arch_idle(), we check if the GPT broadcast clock
event is switched to one shot mode. If the kernel clocksource
is switched from jiffies one to GPT, then we can use GPT
as broadcast event. And switch from local timer to GPT broadcast
event before entering mx6q_wait. Otherwise, kernel will hange
if the SW jiffies clock source is used.
We call clockevents_notify to switch clock source.
* Remove the enable_wait_mode check in local timer setup.
* Always return 0 in GPT v2 timer's set_next_event routing.
All the GPTs are running in free run mode as what driver did.
So we should allow the GPT CNT register roll over to 0 when it
reaches 0xFFFFFFFF. And the next event written to compare register
can less than the current value in CNT.
If we refused to do roll over settings, the kernel will continues
to set_next_event to GPT when the next event is far away and
we return negative value. This is happend when one CPU is in idle
and no timewheel is being expired in short time.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Enable local timer by default. If wait mode is on,
local timer will be shutdown automatically on boot.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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After a cpufreq transition, update the clockevent's frequency
by fetching the new clock rate from the clock framework and
reprogram the next clock event.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
Signed-off-by: Colin Cross <ccross@android.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add a smp_twd system clock which is simple clock
from parent of cpu_clk, and it's rate is half
of the cpu_clk.
This is used for reprograming the twd clock event
after cpu freq is changed.
Also disable local timer setup when wait mode enabled.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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1. add uevent for wm8958 in sabresd
2. change the clock, clko_clk is same as cko1_clk0
Signed-off-by: b02247 <b02247@freescale.com>
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Update the android defconfig for wm8958 mfd and sound driver
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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add wm8958 codec support
Signed-off-by: Gary Zhang <b13634@freescale.com>
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add wm8958 option in defconfig
Signed-off-by: Gary Zhang <b13634@freescale.com>
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Add cpu hotplug support when system entry in earlysyspend.
With this patch, when system entery in earlysuspend, it will
record the online cpus, then hotplut none-bootable cpus,
and in late resume, it will boot up the recorded hotplug cpus.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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This patch removes the IPUv3 overlay framebuffer
reservation.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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When system is going to enter WAIT mode, set PLL1 to 24MHz
so that ARM is running at 24MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Conflicts:
arch/arm/mach-mx6/clock.c
arch/arm/plat-mxc/devices/platform-imx-perfmon.c
drivers/usb/gadget/arcotg_udc.c
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This patch removes the IPUv3 overlay framebuffer memory
reservation.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch checks overlay fb size before reserve fb mem for
it.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Change to discharge both dp and dm
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Only add for lvds1, and the edid i2c address is 0x50.
lvds0 edid i2c is conflict with HDMI edid.
Switch the ldb0/1 di interface to let fb0 initialized with LVDS1.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Should include android_pmem.h and android.h
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Add android pmem device for SABREAUTO.
Add pmem, fbmem command line parser.
Signed-off-by: Prabhu Sundararaj <b36876@freescale.com>
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set GPIO config and disable UART3 DMA.
Signed-off-by: Zhou Jianzheng <B38613@freescale.com>
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the reset value of LPM[1:0] in CCM_CLPCR register is b'01, which means
system will enter into wait mode on next assertion of dsm_request signal.
In order to avoid the system unexpectly enter the wait mode during bootup
we need set the LPM mode to run mode explicity during early boot up phase,
Anytime, we want system to enter the wait mode, the sw procedure is:
mxc_cpu_lp_set(LP_MODE) -> set CCM_CLPCR register -> system enter wait mode
This patch also fix linux kernel reboot stress test on i.mx6dl, without this
patch linux kernel reboot test will fail random with error like this:
[ 12.091220] Bad mode in interrupt handler detected
[ 12.096056] Bad mode in interrupt handler detected
[ 12.100851] Internal error: Oops - bad mode: 0 [#1] PREEMPT SMP
Signed-off-by: Jason Liu <r64343@freescale.com>
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Currently we use 24MHz clock as GPT's clock
source, serial clock can be disabled, it sourced
from high freq clock, gating it can save ~8mA @VDDSOC.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The LDO voltage constraint not printed correctly:
print_constraints: vddpu: 725 <--> 1300 mV at 700 mV fast normal
print_constraints: vddsoc: 725 <--> 1300 mV at 700 mV fast normal
print_constraints: vdd2p5: 2000 <--> 2775 mV at 2000 mV fast normal
print_constraints: vdd1p1: 800 <--> 1400 mV at 700 mV fast normal
print_constraints: vdd3p0: 2800 <--> 3150 mV at 2625 mV fast normal
There due to one typo: << in the code, thus will make the LDO constraint print
not correctly, the patch will make the print correctly as the followings:
print_constraints: vddpu: 725 <--> 1300 mV at 1100 mV fast normal
print_constraints: vddsoc: 725 <--> 1300 mV at 1200 mV fast normal
print_constraints: vdd2p5: 2000 <--> 2775 mV at 2400 mV fast normal
print_constraints: vdd1p1: 800 <--> 1400 mV at 1100 mV fast normal
print_constraints: vdd3p0: 2800 <--> 3150 mV at 3000 mV fast normal
Signed-off-by: Jason Liu <r64343@freescale.com>
(cherry picked from commit 5c2d296401e2ded0cd36f9e651871c6454049de1)
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enable the ov5640 mipi and ov5642 for dual camera in mx6
Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
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Change GPU2D core clock to 480M and use PLL3 as parent
Signed-off-by: Larry Li <b20787@freescale.com>
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None of the workarounds implemented in SW provide a stable solution for
the WAIT mode issue.
For 4.1 release, WAIT mode is disabled by default.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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- Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT.
- IEEE-1588 ts_clk and i2c3 are mutually exclusive, because
all of them use GPIO_16, so it only for one function work
at a moment.
- Test result:
TO1.1 IEEE 1588 is convergent in Sabrelite board.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Conflicts:
arch/arm/mach-mx6/board-mx6q_arm2.c
arch/arm/mach-mx6/board-mx6q_sabresd.c
drivers/mmc/core/bus.c
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on i.mx6dl, gpu2d_axi clock is directly connected to mmdc0
Signed-off-by: Jason Liu <r64343@freescale.com>
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code clean up by removing the dead code in function pfd_set_rate
Signed-off-by: Jason Liu <r64343@freescale.com>
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code clean up by removing the un-expected mfd/mfn/mfi setting
Signed-off-by: Jason Liu <r64343@freescale.com>
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Due to HW limitation, otg is not functional.
So disable the otg host function and only enable otg device
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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* Sabreauto platform only supports spdif in (Rx)
Remove unused Tx clock settings
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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* Sabreauto platform only supports spdif in (Rx)
Remove unused Tx clock settings
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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add ePxP config option
Signed-off-by: Robby Cai <R63905@freescale.com>
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MSL part for ePxP v2 driver
Signed-off-by: Robby Cai <R63905@freescale.com>
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enable max8903 in defconfig.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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add battery support.
support Charger plug in and detect, DC and USB.
support charging status query.
not support voltage reading due to HW design,
to support this will have more efforts so add this later if needed.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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mx6dl do not have 3d shader core,
and 2d core clk is using 3d shader clock.
Signed-off-by: Wu Guoxing <b39297@freescale.com>
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One type error on ov5640_mipi IOMUX configure, fix it.
Signed-off-by: Even Xu <b21019@freescale.com>
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System would be halt, when the default value CTRL_2 is set to
high, change the default value to low.
root cause: System 3V3 would be dragged down to 1.5V for about 4ms.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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One type error on ov5640_mipi IOMUX configure, fix it.
Signed-off-by: Even Xu <b21019@freescale.com>
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