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2013-09-14ARM: mm: Re-enable pageattr.o buildsDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14fixup! arm: tegra: pluto: Modularize board panel fileDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14fixup! ARM: tegra: pluto: set pmic irq type to LEVEL_HIGHDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14fixup! arm: tegra: dalmore: Runtime panel detectionDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: panel: Add platform_device includeDan Willemsen
This header uses platform_device, include it here. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: panel: Add export includeDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: cluster: Remove obsolete tracingDan Willemsen
The old cpu power tracing API was removed by this commit: 43720bd6014327ac454434496cb953edcdb9f8d6 Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14HACK: Disable cpu_volt_cap message to userspaceDan Willemsen
bug 1340826 Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: invalid cpuidle state countAjay Nandakumar
cpuidle state count is being decremented twice for cpus other than cpu0.Due to which state count for other cpus is one. Bug 1327616 Change-Id: Ia3eb05c0ac5c64fdd0d97f0f04b3c6352c49f155 Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/251614 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Tested-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: Move ARM gic.h to include/linux/irqchip/arm-gic.hDan Willemsen
See upstream commit 520f7bd73354f003a9a59937b28e4903d985c420 Change-Id: I50337275d7336e05a2ec0b4978bcd3abd778813c Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: Remove unused includeDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: move ARCH_REQUIRE_GPIOLIBDan Willemsen
Upstream commit e0277f66125686c7112050ba144efd6d759c47c0 moved ARCH_REQUIRE_GPIOLIB to the ARCH_TEGRA choice, so it's no longer required here. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: remove mach .handle_irq for GIC usersDan Willemsen
See upstream v3.9 commit: commit b2e6833c1e390e7902698a1576cc76970ccd55db ARM: remove mach .handle_irq for GIC users Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: delete struct sys_timerDan Willemsen
Make changes necessary for upstream v3.9 commit: commit 6bb27d7349db51b50c40534710fe164ca0d58902 ARM: delete struct sys_timer Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM:tegra: Enable powergate debugfs for all platformsAjay Nandakumar
Enable powergate debugfs for all platforms Bug 1327616 Change-Id: I0217a24202ecc308097f95a3ab3554a6810e4075 Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/251619 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Tested-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: dma-mapping: Add dma_alloc_*at*_coherent()Hiroshi Doyu
Add the version we can specify which IOVA to allocate. Bug 1309498 Bug 1327616 Change-Id: I434171b09e40f888190b696b567d25777c69bb45 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/247938 (cherry picked from commit 063bf38038fa11b2ba0b7af64a2151b74dee8516) Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/250834 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Tested-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: dt: tegra11: Add uart controller dt entryKunal Agrawal
Add uart controller details in the dts file of Tegra114 Bug 1323103 Change-Id: Ie3e7902e450bdbe343457014751526c0d2bd26cb Signed-off-by: Kunal Agrawal <kunala@nvidia.com> Reviewed-on: http://git-master/r/218208 Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/247129 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Tested-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: dalmore: enable HS UART through DTPradeep Goudagunta
-Enabling HS UART 0,1,2 through device tree for Dalmore. -Enable HS UART3 using board platform data if requested from odm-data. Bug 1323103 Change-Id: I43a86c726d07c101bd3c8604499b90612f8b391c Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-on: http://git-master/r/233261 (cherry picked from commit dba9fd3a331823c7be5626e3e0d5f9baa21af983) Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/247125 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Tested-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: dalmore: Enable serial-tegraPradeep Goudagunta
Bug 1323103 Change-Id: Iae6f64f1f0fa3c5c544071c5cdea43e35f41a025 Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-on: http://git-master/r/232990 Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/246725 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Tested-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: Rename HS uart driver namePradeep Goudagunta
Tegra will use serial-tegra as HS uart driver. Bug 1323103 Change-Id: I86c9b46e96cf81896057de59a7afc6e680e6c08e Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/233262 (cherry picked from commit a1fb3b5a3a02626c00f7dd0e295daa55ddaaf2e4) Reviewed-on: http://git-master/r/246724 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Tested-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: config: tegra11_android: Regenerate defconfigDan Willemsen
Ensure that the following are selected: * CONFIG_TEGRA20_APB_DMA * CONFIG_SPI_TEGRA114 bug 1310453 Change-Id: Ia5077ad142ea1a276b23330d71f1cfb8a33766ee Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14HACK Revert "ARM: tegra: dalmore: enable full regulator constraints"Dan Willemsen
This reverts commit 81720be0e212e0e879a1bf9a56247447903ea645. Now the display on my dalmore comes on. Change-Id: I40720067aa75c97e095b4babcb8b3096815b970a Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14HACK Revert "ARM: tegra: sdhci: Pass min,max vcore overrides"Dan Willemsen
This reverts commit fc2ca38aeef3c44c70de4b6915f16bf3ffebd96e. Otherwise we get I/O errors at boot. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14arm: tegra: gmi: Fix driver dependencies for devices on gmi bus.Nitin Sehgal
- nor mapping driver, pca gmi & sram driver could be selected independently. - efs & pflash should depend on nor mapping driver. bug 1294819 Change-Id: I8d201f6aad5ec742ff57d2c11a2507b2bc4f5a8d Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com> Reviewed-on: http://git-master/r/235036 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-14arm: tegra: Fix incorrect register usage in lp1 suspendKarthik Ramakrishnan
The register r0 is being used as TEGRA_CLK_RESET_BASE address, and r5 is used as tegra3_sdram_pad_save register. These registers were used incorrectly here. Bug 1270351 Change-Id: I9fe39ab052fa875e809d7b33a5ae346060d3090f Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> Reviewed-on: http://git-master/r/236472 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14ARM: tegra14: clock: Allow switch to G CPU on PLLXAlex Frid
Enabled PLLX as CPU clock source immediately after LP CPU to G CPU cluster switch when cross-over rate is below DFLL usage range, and PLLX was the last G CPU clock source (before this commit DFLL was elected as target source after cluster switch to G CPU always). Ported from tegra11 commit 835d3c8b14949b853f198ac6545d7e1edda270f0 Change-Id: Id42f74f416f35cdf2afbe2574924baa19a59c5d7 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/236577 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2013-09-14ARM: tegra: dvfs: Change CL-DVFS tuning orderAlex Frid
Change CL-DVFS tuning order: when tuning low: tune dfll low, then tune target module trimmers low when tuning high: tune target module trimmers high, then tune dfll high (was complementary order in both cases above). Bug 1291764 Change-Id: Ic1a3850790089975e045cc9efcceb1dc06513b40 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/236576 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra: dvfs: Invalidate CL-DVFS request when disabledAlex Frid
Invlidated frequency request when CL-DVFS is disabled. Made sure that the first request after enabling CL-DVFS always includes regulator undershoot guard-band (i.e., do not use stale across disabled state frequency request to evaluate direction of the change). Bug 1285525 Change-Id: Ib3a885b7add43b14e21df8cce974f3d5ea068cb0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/228515 (cherry picked from commit 03f597b4652b6c4858d04cf319ced21b7e4013e8) Reviewed-on: http://git-master/r/236575 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra11: clock: Allow switch to G CPU on PLLXAlex Frid
Enabled PLLX as CPU clock source immediately after LP CPU to G CPU cluster switch when cross-over rate is below DFLL usage range, and PLLX was the last G CPU clock source (before this commit DFLL was selected as target source after cluster switch to G CPU always). Bug 1291764 Change-Id: I55c75a819f4f6e0af89f00fa01504cb5349c378f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/230054 (cherry picked from commit 835d3c8b14949b853f198ac6545d7e1edda270f0) Reviewed-on: http://git-master/r/235692 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra11: dvfs: Update AP40 Vmin in DFLL modeAlex Frid
Minimum voltage in DFLL mode for AP40 sku is different (0.9V) from all other skus (1.0V) that share the same cpu dvfs tables. Updated AP40 Vmin respectively. Bug 1291764 Change-Id: I3f40f24bc68c376d18b09b2f55987c05164cc05d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/236574 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra11: dvfs: Update dvfs tablesHoang Pham
Change the tune high voltage to 1050mV Bug 1291764 Change-Id: I5a6ab3910b56615f0075d2e7e29220456eb986b9 Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: http://git-master/r/233879 (cherry picked from commit 4d23ea742f932edd3654473225b946fd5d3d8245) Reviewed-on: http://git-master/r/236573 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra11: dvfs: Set CPU Vmin in DFLL mode 1.0VAlex Frid
Bug 1291764 Change-Id: I84a6854b0d7c85e602a6bc21d3fcb497613e5cae Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/230034 (cherry picked from commit 31d387d6e572e5241eca786819f0af444aef8da7) Reviewed-on: http://git-master/r/236572 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra11: dvfs: Update CPU dvfs tablesAlex Frid
Bug 1291764 Change-Id: I92c652e9ecbec366c017ab2eda0e51b1dd42cb17 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/230033 (cherry picked from commit 8c42909312f5082d3e62f0fbc7b0556e7aed099d) Reviewed-on: http://git-master/r/236571 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14arm: dts: pluto: Add panel gpio DT supportAnimesh Kishore
- DT driver support for panel gpios. - DT gpio entries for default pluto panel. Bug 1172236 Change-Id: I09215d4ecee25d4e01b1345cc116e6c95378283f Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/235009 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2013-09-14ARM: tegra: bbc: remove unused sysfs APIsNeil Patel
Several sysfs attributes were unused and are being removed: - iso_reserve and iso_realize attributes are removed as the bbc always reserves/realizes in one remote request - removing the read capability for i_max_store since the EDP driver provides attributes to check this for all clients - removing bbcllr latency allowance attribute since LLR port LA is hardcoded in hw Bug 1303605 Change-Id: If2fed4ebe2eefb9d177d7abb983d4f502296470e Signed-off-by: Neil Patel <neilp@nvidia.com> Reviewed-on: http://git-master/r/228506 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2013-09-14power: max77665-charger: remove extcon support from charger driverLaxman Dewangan
Remove extcon support from charger driver and register power-supply extcon driver for the power supply update. The charging current is now configured through the charging regulator through regulator framework. Change the driver initialisation sequence so that the charger driver get initialised before usb-udc driver. Change-Id: Ia01ae1a9240281adab28fec7062faa63c918f004 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/234257 (Cherrypicked from 97c9137413b528956f799254a156a242c114c9fe) Reviewed-on: http://git-master/r/236742 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: tegra: pluto: add max77665 charging regulator consumerLaxman Dewangan
MAX77665 charger driver expose the charging functionality through regulator framework. Add the consumer of this regulator. Change-Id: Idd4399c12744de2faa0151368fefb81259c4f4c5 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/234256 (Cherrypicked from b97d6ada077324190f8b5abb9094de180e76bf86) Reviewed-on: http://git-master/r/236741 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: tegra: remove CPU power lim from EDP debugfsSivaram Nair
This attribute is moved under the sys EDP debugfs - hence, removing it from here. Change-Id: I3167a4121a9260754b51230b417317e6c2ddee4d Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/236269 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: tegra: macallan: fix Coverity issueDeepak Nibade
- fix uninitialized scalar variable Coverity id : 23406 Bug 1046331 Change-Id: Iddc42251f7ecfd2e406eadd6af64b6b641cf1464 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/235482 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2013-09-14ARM: tegra: sdhci: Pass min,max vcore overridesPavan Kunapuli
Pass minimum and maximum vcore override voltages to be used during auto tuning. Bug 1246712 Bug 1294659 Change-Id: I9d038dcec32fc3592103ab459aa99591ea4a7106 Reviewed-on: http://git-master/r/212683 Signed-off-by: R Raj Kumar <rrajk@nvidia.com> Reviewed-on: http://git-master/r/234885 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: tegra148: clock: Update cpu to emc rate ratioPritesh Raithatha
Bug 1285880 Change-Id: I545195aca15b5ec24228bd4d82cc3ee5d9dcc99d Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/233003 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: tegra14: pm: Keep PLLP on during LP1BBPrashant Malani
Modem can run off of PLLP. Therefore we always keep PLLP on while entering LP1BB Bug 1299404 Bug 1302597 Change-Id: I56a4178e954188d7e1c73058933a1eddc2e24b8d Signed-off-by: Prashant Malani <pmalani@nvidia.com> Reviewed-on: http://git-master/r/236363 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2013-09-14ARM: tegra: ceres: move battery model data to common INI fileLaxman Dewangan
Move battery model data to the common INI file in place of keeping it in c file. This way, it will simple and easy to refer the different battery data at single place. Change-Id: I7ff721f86832f12aa7173ca7f0689ff670f77483 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/235835 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2013-09-14ARM: tegra: macallan: add Yoku 3900 battery data for Max17048Laxman Dewangan
Just add the Yoku 3900mA battery data for Macallan. Details of model data: Battery: Yoku current: 3900mA system shutdown voltage 3.0V. Model: Max17048 Macallan will still use the Yoku4100 as default. Change-Id: I98df0a3fdb2ded9a501812ecc8ffb924fb252545 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/235017 Reviewed-by: Automatic_Commit_Validation_User Reviewed-on: http://git-master/r/235834
2013-09-14ARM: tegra: pluto: move battery model data to common INI fileLaxman Dewangan
Move battery model data to the common INI file in place of keeping it in c file. This way, it will simple and easy to refer the different battery data at single place. Change-Id: Ie874effd679ddf6a5f24c10e2f11a4623866047d Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/234769 (Cherrypicked from commit d0a22eb7f117fb6bfe68022d0541134a8c0bf68e) Reviewed-on: http://git-master/r/235833 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2013-09-14ARM: tegra: macallan: move battery model data to common INI fileLaxman Dewangan
Move battery model data to the common INI file in place of keeping it in c file. In this way, the model data will share the same structure and avoid the duplicaton of table across board files. Change-Id: I33aa45b1fbed48b6ad15512398949f390c3bbabe Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/234571 (Cherrypicked from 7bb76ff9095a6bab220af5442063a503d174e2bd) Reviewed-on: http://git-master/r/235832 Reviewed-by: Automatic_Commit_Validation_User
2013-09-14arm: tegra: macallan: add ini file for yoku 4100mAh batterySyed Rafiuddin
addition of battery chracterization data to max71048 fuel-gauge driver Bug 1283683 Change-Id: I6cf37a3d3720f98de0e58f1027bb88e712641e92 Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com> Reviewed-on: http://git-master/r/232077 (Cherrypicked from 048954eaaa6accbb97e41e856d3b6bb04d5382e0) Reviewed-on: http://git-master/r/235831 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-14ARM:tegra: Add support to parse touch idXiaohui Tao
Support to parse touch panel id for roth Change to parse touch vendor id for ceres and pluto Bug 1253012 Change-Id: I902a1a63efc030cb4b4e82e7301c00027c8e950c Signed-off-by: Xiaohui Tao <xtao@nvidia.com> Reviewed-on: http://git-master/r/221647 Reviewed-on: http://git-master/r/218964 (cherry picked from commit 29178237b3073b45569dcec2fc85bdd7491a1f25) (cherry picked from commit a79f45c5357191fa8da61c8fefe3a79bef8afadb) Reviewed-on: http://git-master/r/229038 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: tegra: enable Tskin-induced thermal shutdownHyungwoo Yang
This change adds a trip point which shutdowns device when Tskin reaches to the trip point. Default value of the trip point is 57C. Bug 1274052 Change-Id: Ibebd93ba3b83d750cd34bb01f35ef2695ab8c975 Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com> Reviewed-on: http://git-master/r/221813 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com> Reviewed-by: Edward Riegelsberger <eriegels@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2013-09-14arm: tegra: macallan: enable OC4 interruptTony Liu
Following are changes: -provide base interrupt for soc therm to support OC interrupt -enable CPU/GPU throttling through OC4 interrupt Bug 1255452 Change-Id: I19d0194fc411df4da73d2f6dc5abc0c5ab7937a9 Signed-off-by: Tony Liu <tonliu@nvidia.com> Reviewed-on: http://git-master/r/225550 (cherry picked from commit f9e520dec8fb4bf0628f87367841936586fc15fa) Reviewed-on: http://git-master/r/235799 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-02 18:10:25 +0000