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2009-09-02Add extra checks to ARM unwinder to avoid tracing corrupt stacksCatalin Marinas
There are situations where the unwinder goes beyond stack boundaries and unwinds random data. This patch moves the stack boundaries check after the unwind_exec_insn() call and adds an extra check for possible infinite loops (like "mov pc, lr" with pc == lr). The patch also fixes a bug in the unwind instructions interpreter. The 0xb0 instruction can only set PC to LR if this wasn't already set by a previous instruction (this is used on exceptions taken while in kernel mode where svc_entry is annotated with ".save {r0 - pc}"). The patch also corrects the FP register number for Thumb-2. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Tony Lindgren <tony@atomide.com>
2009-09-02ARMv7: Make SWP always enabled on Cortex-A9Catalin Marinas
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-09-02ARMv7: Mark PTWs outer non-shareable on SMPCatalin Marinas
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-09-01ARMv6: Updated the BE-8 patch to be in sync with the mainline kernelCatalin Marinas
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-09-01Thumb-2: Pass -mthumb in AFLAGS_THUMB2Catalin Marinas
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-09-01Thumb-2: Fix unpredictable "lsr r6, pc, #..." in kernel/head.SCatalin Marinas
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-05-05Fix the Thumb-2 entry code when TRACE_IRQFLAGS is enabledCatalin Marinas
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-04-30arm: update realview defconfigs to use smsc911xSteve Glendinning
Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
2009-04-30arm: convert realview platform to use smsc911xSteve Glendinning
Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
2009-03-31ARMv7: Enable the ACTLR.FW bit to enable TLB ops broadcasting on SMPCatalin Marinas
By default, this bit is turned off and TLB and cache operations aren't automatically broadcast to the other CPUs in an SMP system with Cortex-A9. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10RealView: Add mdelay() to realview_clcd_setup() for PB1176Colin Tuckley
There is a known fault which is under investigation and the patch is a workaround. Signed-off-by: Colin Tuckley <Colin.Tuckley@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Eviction Buffer not empty after Cache Sync on the L220 cache controllerCatalin Marinas
This patch adds the workaround for the 484863 L220 erratum. The writing of the L220 registers is done with a SWP rather than STR instruction. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Workaround for Cortex-A8 erratum 451034Mans Rullgard
On Cortex-A8 r1p0 and r1p1, executing a NEON store with an integer store in the store buffer, can cause a processor deadlock under certain conditions. Executing a DMB instruction before saving NEON/VFP registers and before return to userspace makes it safe to run code which includes similar counter-measures. Userspace code can still trigger the deadlock, so a different workaround is required to safely run untrusted code. See ARM Cortex-A8 Errata Notice (PR120-PRDC-008070) for full details. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Data written to the L2 cache can be overwritten with stale data on Cortex-A8Catalin Marinas
This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It configures the L2 cache auxiliary control register so that the Write Allocate mode for the L2 cache is disabled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Processor deadlock when a false hazard is created on Cortex-A8Catalin Marinas
This patch adds a workaround for the 458693 Cortex-A8 (r2p0) erratum. It sets the corresponding bits in the auxiliary control register so that the PLD instruction becomes a NOP. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Stale prediction on replaced interworking branch on Cortex-A8Catalin Marinas
This patch adds the workaround for the 430973 Cortex-A8 (r1p0) erratum. The BTAC/BTB is now flushed at every context switch. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Spinlocks using LDREX and STREX instructions can livelockHarry Fearnhamm
According to the ARM11MPCore Erratum 351422 (r0p0), under extremely rare conditions, in an MPCore node consisting of at least 3 CPUs, two CPUs trying to perform a STREX to data on the same shared cache line can enter a livelock situation. This patch adds variable spinning time to the locking routines. Signed-off-by: Harry Fearnhamm <Harry.Fearnhamm@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Workaround for the global I cache invalidation ARM1136 ErrataCatalin Marinas
Errata 411920 - Invalidation of the Instruction Cache operation can fail. This Errata is present in 1136, 1156 and 1176. It does not affect the MPCore. This patch implements the ARM Ltd recommended workaround. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Enable partial low interrupt latency mode for ARM1136Catalin Marinas
This patch is a workaround for the 364296 ARM1136 r0pX errata (possible cache data corruption with hit-under-miss enabled). It sets the undocumented bit 31 in the auxiliary control register and the FI bit in the control register, thus disabling hit-under-miss without putting the processor into full low interrupt latency mode. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Add RealView-ICE DCC ethernet and console driverRobert Walker
This patch adds support for console and Ethernet over DCC using RealView-ICE to Linux 2.6.28-arm1. Signed-off-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10ARM Ltd's reworked oprofile supportJon Callan
Signed-off-by: Jon Callan <Jon.Callan@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Thumb-2: Add IT instructions to the kernel assembly codeCatalin Marinas
With modified GNU assembler, these instructions are automatically generated. This patch is to be used if such gas isn't available. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Thumb-2: Pass a Thumb-2 address to the secondary CPUs to jump toCatalin Marinas
This patch sets bit 0 in the startup address passed to the secondary CPUs so that they branch into Thumb-2 mode. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Thumb-2: Make the uImage entry an odd numberCatalin Marinas
This allows U-Boot to branch to the kernel in Thumb-2 mode via "mov pc, lr". Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Thumb-2: Add Thumb-2 support to the build filesCatalin Marinas
This patch adds the necessary entries to the Makefile and Kconfig files for building the Thumb-2 kernel. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Thumb-2: Add support for loadable modulesCatalin Marinas
Modules compiled to Thumb-2 have two additional relocations needing to be resolved at load time, R_ARM_THM_CALL and R_ARM_THM_JUMP24, for BL and B.W instructions. The maximum Thumb-2 addressing range is +/-2^24 (+/-16MB) therefore the MODULES_VADDR macro in asm/memory.h is set to (MODULES_END - 8MB) for the Thumb-2 compiled kernel. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Thumb-2: Implement the unified boot codeCatalin Marinas
This patch adds the ARM/Thumb-2 unified support for the arch/arm/boot/* files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Thumb-2: Implement the unified VFP supportCatalin Marinas
This patch modifies the VFP files for the ARM/Thumb-2 unified assembly syntax. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Thumb-2: Implement the unified arch/arm/lib functionsCatalin Marinas
This patch adds the ARM/Thumb-2 unified support for the arch/arm/lib/* files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Thumb-2: Implement the unified arch/arm/mm supportCatalin Marinas
This patch adds the ARM/Thumb-2 unified support to the arch/arm/mm/* files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Thumb-2: Implementation of the unified start-up and exceptions codeCatalin Marinas
This patch implements the ARM/Thumb-2 unified kernel start-up and exception handling code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Thumb-2: Add macros for the unified assembler syntaxCatalin Marinas
This patch adds various C and assembler macros that help with using the unified assembler syntax for compiling files to either ARM or Thumb-2 modes. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10nommu: Do not set PRRR and NMRR in proc-v7.S if !MMUCatalin Marinas
ARMv7-R profile CPUs do not have these registers. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10nommu: Fix compressed/head.S to not perform MMU specific operationsCatalin Marinas
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10nommu: Do not allow REALVIEW_HIGH_PHYS_OFFSET if !MMUCatalin Marinas
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10nommu: Add #ifdef CONFIG_MMU around the PTE sanity checksCatalin Marinas
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10nommu: Include asm/setup.h in arch/arm/mm/nommu.cCatalin Marinas
This is needed for the struct meminfo definition. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10nommu: Add noMMU support to the DMA APICatalin Marinas
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10nommu: Enables to select noMMU modeHyok S. Choi
MMU option is now selectable. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
2009-03-10nommu: Remove the memory_start/end variables from ARM page-nommu.hCatalin Marinas
These variables do not seem to be used anywhere in the kernel. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10nommu: Do not override the CP15 control reg value returned from initfuncCatalin Marinas
The patch removes the "mrc" instruction in head-nommu.S overriding the r0 register containing the value to be written in the CP15 system control register. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10nommu: ptrace supportPaul Brook
The patch below adds ARM ptrace functions to get the process load address. This is required for useful userspace debugging on mmuless systems. These values are obtained by reading magic offsets with PTRACE_PEEKUSR, as on other nommu targets. I picked arbitrary large values for the offsets. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-03-10nommu: Add MMU-less support for RealView/EBCatalin Marinas
This patch redefines the IO_ADDRESS macro. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10nommu: Add MMU-less support for Integrator platformsCatalin Marinas
This patch redefines the IO_ADDRESS macro in include/asm-arm/hardware.h. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10nommu: Remove the context.id from asm-offsets.c when !MMUCatalin Marinas
There is no MMU context switching on MMU-less systems. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10nommu: Fix the fault processing for the MMU-less caseCatalin Marinas
The patch adds the necessary ifdefs around functions that only make sense when the MMU is enabled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10Allow the L2x0 cache controller to be already initialisedCatalin Marinas
This patch checks whether the controller is already initialised before configuring and enabling it (for situations where Linux is running in non-secure mode and the controller was already enabled). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10RealView: Initialise the L2 cache via early_initcallCatalin Marinas
This is required on SMP systems where the L2 cache is already enabled when the kernel is started (e.g. in non-secure mode) and boot_secondary() needs to call outer_clean_range(). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10RealView: Toggle one LED per CPUCatalin Marinas
If CONFIG_LEDS is enabled, it makes more sense to toggle one LED per CPU in SMP systems rather than a single LED for all the CPUs. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-03-10RealView: Allow CONFIG_LEDS on this platformColin Tuckley
Signed-off-by: Colin Tuckley <Colin.Tuckley@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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