Age | Commit message (Collapse) | Author |
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Enable registration of suspend_ops with kernel. This will enable
platform specific low power states based on odm query.
Change-Id: Ie38fc67fe76124d21f0f6ca107a89efd9e4ec8b1
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We implement suspend_ops->valid, suspend_ops->begin,
suspend_ops->enter and suspend_ops->end.
For suspend_ops->begin :
Check if CPU1 is in reset or not.
If not, reset it and maintain this state.
For suspend_ops->end :
Check if CPU1 was reseted by suspend_ops->begin.
If yes, take it out of reset.
For harmony board, add a timed wake lock as a WAR.
For suspend_ops->enter :
Do a odm query for lowest power state.
Call the appropriate low power state (LP1/LP0)
routine based on SOC type.
Change-Id: I6f4be75978573bba94e95723c023abc091e06d1e
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into android-tegra-2.6.29
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Bug 653500
This is an issue in RM transport.
This is because of sleep time when the buffer is not ready to send msg.
The sleep of 1msec is taking 10 to 20msec time as linux jiffy time is 10msec.
This fixed by using the polling for one jiffy time and using sleep afterwards.
Change-Id: I6656dc5e1e4cca20b115cd6b489e6a7f95944f0a
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This changes is applicable to harmony odm.
Change-Id: I85d744a80b71533576c3896ebd21f0b34ea5de91
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android-tegra-2.6.29
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Moved EMC DFS low corner back to 50MHz (from 18MHz - affects LPDDR2
platforms). This is done since new AudioMixer unable to reach 18MHz
LC - optimization is in progress (bug 654473).
Change-Id: Iaf9acf0160dd3c07a1ff0a0bacd4bdc36d620e2c
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Nand was seen as active device during suspend as Ddk Nand suspend code
was getting bypassed. Ddk Nand Suspend clocks call disables clock after
any operation. Later when suspend API found the clock disabled
RM voltage control calls were getting skipped. Modified suspend
implementation to use new suspend flag that skips suspend call
only when suspend is done once.
Tested on: harmony. Nand no longer active when entering lp1
Reviewed by: vbyravarasu
Change-Id: Iebda224a5b4eaeed77186abd096f67ee6473966e
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Bug 642072: Power Aware NvRM Daemon
- Added /sys/power/nvrm/notifier as an interface to nvrm_daemon.
- Added pm_notifier, which notifies nvrm_daemon.
- Apply p4 change 5506101 with or before this change.
Change-Id: I8e170389661be9a1c55fbd37b95e0c5c276506b3
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To avoid the re-enumuration on wakeup from low power state, USB controller
context is saved before entering into suspend state and on resume the
stored context is restored. To restore the context properly, USB controller
needed to be programmed in the steps provided by the hardware team. With
this on wakeup, no re-enumurtion is happening.
Bug 594395 : Fast Wake for USB Modems
Bug 635371 : [AP20 \ Android] Baseband 3rd Party driver power management
in Android
Tested on : Android/whistler with suspend/resume framework enabled.
Tested for USB2 External ULPI + USB3 UTMI ports on Whistler
Tested for USB3 UTMI port on Harmony
Change-Id: Iba1b1a199d83c5b03bed192282e826996518d7b7
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android-tegra-2.6.29
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into android-tegra-2.6.29
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with the change to allocate messages < MAX_SIZE on the stack
inside the dispatcher, there were actually 2 on-stack copies
of the message being maintained: one in the dispatcher, and
one in the RM transport code itself.
the transport code copied the message in order to prepend
a 3-word header; however, since the entire message was then
copied into a memory handle to send it to the AVP, the
internal copy is unnecessary; the message header can be
written directly to the memory handle and then the buffer
provided by the dispatcher can be copied directly into
the memory handle
Change-Id: I3a748192d7e45445bc821456e170670cc3fb0e98
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Change-Id: I82dbf8c0a0aefcbb77b9596e46858f7c79376b9c
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The LP1 power state serves as a bridge between LP0 and LP2
states. In the LP1 state, memory is put in self refresh, plls
are turned off aggressively, and drivers are shutdown.
Change-Id: Ia02de8644d4c091aa5ccd012b287bdb55e7224e8
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Added spinlock primitives to NvOs.
Converted PMC scratch registers access mutexes to spin-locks.
Change-Id: I862baf4d3a7a8fcdf1e8552356805afd4ac897c3
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Moved EMC DFS low corner from 50MHz to 18MHz (affects LPDDR2 platforms).
It is possible now, since EMC BCT configuration bug 632015 is fixed.
Change-Id: I3a5bc3ebb7fb5fac1e70327970b6a215152d1cab
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This change simply calls the appropriate suspend/resume APIs of
nvrm_kernel respectively. Return -1 in case of error.
This change is must when we enable system power management.
Change-Id: I698f7d7d3daf9eeb63872ddf2f8a216d3f3e9166
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android-tegra-2.6.29
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into android-tegra-2.6.29
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android-tegra-2.6.29
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change the buffer size from the default (4KiB) to 16KiB. testing has
shown that the additional buffer size dramatically improves file
transfer performance on Harmony
Change-Id: Ibbf917daffafab6bd7544d89ec111b15dfdb42df
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Bug 650789
Bug 650790
The performance drop was because of moving RM transport into kernel.
After moving it into kernel, for every transport API call, there is
an additional overhead of allocating and freeing memory. This is causing
the performance drop. As the message buffer's max size is 256 bytes,
This performance issue is fixed by using buffer allocated on stock instead
of NvOsAlloc buffer.
Also removed unnecessary nvrm_rpc.h file.
Updated code to allocate memory from heap, if the message size is bigger
than stack buffer.
Change-Id: I9ec01a2bf4a97623446424a6b6abddb869e6f7a6
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on VIPT, ASID-tagged, instruction caches (as are used on most ARMv7A
implementations), invalidating the kernel's instruction cache when
a VM_EXEC page is modified by flush_ptrace_access is insufficient,
since the physical address will be mapped with a different virtual address
and a different ASID in the child process being modified.
when debugging, particularly on SMP systems, this can result in breakpoints
triggering SIGILL errors. the appropriate fix this is documented on
page b3-24 of the ARMV7 architecture reference manual: invalidating the
entire instruction cache.
additionally, incorporate some feedback RMK made about commit
d289f584b9a0be78232e1c8c5844eaaa211aa984.
Change-Id: I0eef82d69fc802c447479fa40384c21222bc32ea
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Implement the enable and disable handlers introduced in the mmc_ops structure.
Use the enable and disable handlers for dynamic clocking of SD memory devices.
SD clock is enabled when the sdhci host is claimed and clk is disabled when
host is released.
Use delayed suspend for better performance.
Change-Id: Ied5e0f00c41abd4f6d0918405356a9983ae06552
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Updating the capability structure to support the uart controller
version 1.2
Updating the relocation table entry for the uart with version number
as 1.2.
Bug 627427 Ap20 UART FIOF triggers are not same as the AP15.
Change-Id: Ia1f676f1d9401008a3958bc8743252ea2cc61ddc
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CONFIG_HIGHMEM (support for > ~600MiB RAM) is enabled by default for
Harmony with this change.
Change-Id: I510a9bff6fb1a98137c24d5790bb0b526a5c553e
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the drivers are written to behave correctly with writecombined memory,
rather than SO, and SO mappings are really, really slow
Change-Id: I6ab9e4f506bbefed5d6d0ec7de36b78ee3b39c42
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Include the function prototype for the private API that
was not added.
tested with local compilation for android.
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android-tegra-2.6.29
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android-tegra-2.6.29
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Change-Id: Iba87dc237961781bd301a782e0160d4addea0ab6
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Presently, NvOdmQueryLowestSocPowerState() for harmony returns state
as active. Changing this to suspend.
This is required when we will enable the RM power management.
Change-Id: I85112372a27ba9f176108fd18108af8507ac6e43
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Added stub audio codec in alsa soc driver Removing platform
dependent source files. ALSA driver is not doing audio codec
initilization. It happens in audiofx. Got rid of unwanted
I2C prints which were coming from wm8753 reg_write function.
For bug 650664 Getting error while booting
NvRmI2Ctransaction Failed:No I2C
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Change-id: I8225d867ee48c" into android-tegra-2.6.29
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the PL3x0 outer cache controllers are largely register-compatible with
the L2X0 controllers; however, the new controllers support atomic
maintenance operations, rather than mandating a polling loop inside
an IRQ-safe spinlock.
this change significantly reduces (>50%) the number of processor cycles
spent performing outer cache maintenance, which has shown up as a hot
spot in a number of places (USB, MMC, graphics rendering, etc.) on
Tegra 2 processors
Change-Id: I7e4f37ceea17241e8767ffea419a7751eae5eb23
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prepare the tegra initialization routine for an upcoming change to
the L2 cache code which will move from using CONFIG_CACHE_L2X0 to
CONFIG_CACHE_PL3X0 in order to improve performance
Change-Id: Icd2b6836682e5f76427b63f9b7785318e9547c07
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in order to implement user vs super-user protections for the nvmap
functionality, multiple device nodes need to be created with separate
file operations, similar to the mem vs kmem separation.
since nvmap is conceptually similar to the other "mem" class devices,
the multiple device nodes are added as new minor numbers in the mem
class, and the existing platform driver registration is removed.
Change-Id: Ie260e4c56679682133d90a69c0985eaaa5a4d071
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devices"" into android-tegra-2.6.29
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android-tegra-2.6.29
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This reverts commit 179fa807239b85a471b046a5ba75dce7c0f68dec.
Need to add dynamic clocking the right way, i.e. as part enable/disable
mmc_ops handler. Commit to follow soon.
Change-Id: I74245b0c7ba9da5c839b08fbe7dce293080a06a4
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Change-id: I8225d867ee48c
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android-tegra-2.6.29
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