Age | Commit message (Collapse) | Author |
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In imx8mq-evk DTS both AUDIO PLL rates are configured, so SPDIF1
pll8k and pll11k clocks can be set accordingly.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 77696d672be5907cc2dff8e20800938e87a174e2)
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Disable PHY eee mode in default to make ptp synchronized time
much more restricted in convergent range.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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add the hyperbus related configs in defconfig
Signed-off-by: Han Xu <han.xu@nxp.com>
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add dedicate dts for hyperbus on i.MX8QXP
Signed-off-by: Han Xu <han.xu@nxp.com>
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Pcie driver power-on-gpio pin to control EP device's power,
firstly power down, then power up when it registers pcie port.
So using the pin for PCIe wlan EP device is better.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 9d34ebb725b192c436a1ce4490b43d0bd21eddc3)
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No need to set the 32KHz PIN except pcie brcmfmac driver
is loaded that requires to reserve these pin groups for
pin->init_state and pin->idle_state to support multiple
differents wlan cards.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 84333ffff3efacefb84a18adee99d40c89a4a754)
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Revert below upstreaming patch which broke SPI5 dma since ram
script used for ecspi to workaroud ERR009165 and spi driver
changed to XCH mode instead of SMC.
Revert "ARM: dts: imx6q: Use correct SDMA script for SPI5 core"
This reverts commit df07101e1c4a29e820df02f9989a066988b160e6.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit 443e65efad14aa3fe1c99ead8fac10ec856b7e44)
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Update i.MX6DL opp table according to i.MX6DL automotive
datasheet Rev.9, 11/2018, it adds 996MHz set-point as below:
LDO enabled(min value):
996MHz: VDDARM: 1.275V, VDDSOC: 1.175V;
792MHz: VDDARM: 1.150V, VDDSOC: 1.150V;
396MHz: VDDARM: 1.125V, VDDSOC: 1.150V;
Adding 25mV to cover board IR drop, for LDO enabled
mode of 996MHz, as the max value of LDO output can NOT
exceed 1.3V, so 25mV is NOT added for VDDARM.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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Add interrupt and related pinctrl properties for ADV7535,
the interrupt can be used for hotplug, edid ready and etc
in the adv bridge driver.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 23141ea22f44fcd87ed8bc2d130776b07a94d4e3)
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Introduce inmate linux support for jailhouse, we need to benchmark
inmate OS, so choose linux. The clock/pin are preconfigured by 1st
root cell linux.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 00bf8b5eea2213896acf4e244ef1b63fb7abea85)
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Because we add the partition reboot function, and assign all flexcan
pins to M4, A core cannot access flexcan pins for now.
LPUART3 uses flexcan pins before, so disable it to avoid this error:
imx8qxp-pinctrl iomuxc: pin_config_set op failed for pin 110
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
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Add the model name accordingly for imx7ulp EVKB board since
the machine name and/or compatible may be used by user.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Add dma support for lpspi0 and lpspi2 modules on i.MX8QXP board.
Ensure the lpspi does not use cs-gpio in slave mode.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
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Since RPMSG switches to use LSIO's MU instead of M4's MU,
the LSIO MU's irq is inside GIC IRQ domain, NOT in intmux
irq domain, so no need to power on intmux early during system
resume.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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With current code, the index are stored in an array at their common index,
ie jr0 store at index 0, jr1 at 1, ...
It force to use buggy mechanic to compute it and is not scalable.
This patch removes the mechanic of computation of hardware register
addresses and the notion of first_jr_index.
Instead the first JR available is set to index 0 of the table and so on.
Legacy code was retrieving the index of the first jr to access registers.
With this new way, we simply always access the first jr.
This is working because after the configuration of the JR in ctl
(enable_jobrings), the driver checks that there is at least 1 JR.
Without this, we could create segfaults.
Fixes: e9688f0f05e0 ("MLK-15473-1: crypto: caam: Add CAAM driver support for iMX8 soc family")
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
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We are currently using SC_R_LAST as a marker for imx8 power domain tree
nodes without a resource attached. This value is compiled into dtb as
part of the linux build and used by uboot.
The SC_R_LAST constant changes frequently as SCFW resources are added
(by design) and every time we need to update linux and uboot headers
together or boot can fail.
Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE
defined to be 0xFFF0.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Fix lvds-pwm usage, it needs to be under vehicle_rpmsg_m4 node for
android auto.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Need to change the default HDMI TX clocks to 800 MHz for DPLL and 100 MHz
for bus.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
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Until now, the DSI PHY_REF clock was by default ON in SCFW, which made
this clock unusable in kernel, therefore, this clock was set as
CLK_DUMMY in DSI device nodes.
Sinnce this clock was set to OFF in SCFW, now it can be used from
kernel, so add it to device nodes so that the driver can use it
properly.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Until now, the DSI PHY_REF clock was by default ON in SCFW, which made
this clock unusable in kernel, therefore, this clock was set as
CLK_DUMMY in DSI device nodes.
Sinnce this clock was set to OFF in SCFW, now it can be used from
kernel, so add it to device nodes so that the driver can use it
properly.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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When system resume from VLPS mode, DDR IO must be restored
before mmdc out of the self-fresh mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Tested-by: Anson Huang <Anson.Huang@nxp.com>
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These CAN related regulators will be handled when kernel boots. However,
these regulators which aren't used by any devices will be disabled by the
regulator framework. So, the pins in these regulators will be non-active
status. This causes the CAN module cannot be used in M4 side.
So, disable these regualtors for 8QM/QXP, and let M4 handles these.
Suggested-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
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Passthrough lvds pwm, otherwise dom0 will panic when reboot if
domu started and shutdown, because LVDS_1_PWM_0 is assigned
to domu and when domu shutdown, the resource will be powered
off, however dom0 still think it is powered on.
since lvds1_pwm is expected for domu, so let's passthrough it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Move the emmc/lpuart/sdcard/sensor/spi-slave testing features
from EVK to EVKB board.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
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The IPG clock is introduced for i2c0 and i2c2 nodes in order to do
properly clock gating/ungating for i2c0 and i2c2.
'ipg' clock drives the access to the device iomapped registers,
so with this patch we are now able to read I2C registers.
Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
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Change-Id: I5837a5d54e2e27503b532b811d477f1d142b2b99
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Change-Id: I8fb3b2515b6fa02cbb7c6849fd0661e4f3f66ee7
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Change-Id: I410909ce69f79846c8956c185570af2e933c829a
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Change-Id: Ic43bc3086562edc513f125605d416fe928c12135
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Change-Id: I268fd5d2bf039699ecdcab752146bc191209f046
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Change-Id: I55f88e103a987bc8adaf2634026031d1fbc1e0b9
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Switch to use rpmsg i2c to support android auto, because
android auto change to use rpmsg i2c.
Also add the alias node to let m4 could use it successfully, because
M4 side use the alias id as the BUSID.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
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The resources are wrongly added.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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There are differences between the output of `make savedefconfig` and the
arm64 defconfig. This happens because CONFIG_I2C_RPBUS=y depends on
CONFIG_RPMSG=y so the latter doesn't have to be explictly selected.
Fixes: b0ee196e5bdf ("MLK-20940-4 ARM64: defconfig: Add RPBUS and RPMSG config")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Joakim Zhang <qiangqing.zhang@nxp.com>
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Since CONFIG_IR_GPIO_CIR=y depends on RC_CORE we shouldn't explicitly
define CONFIG_RC_CORE=y in defconfig, otherwise it generates a
difference between the output of "make savedefconfig" and the actual
defconfig.
Fixes: 35c88640b846 ("MLK-20946-3: arm64: defconfig: add IR support for imx8")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Joakim Zhang <qiangqing.zhang@nxp.com>
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Cleanup the resources that not could be set SID and remove the UNUSED
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
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Update domu car dts according to android auto changes.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
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When resources are owned by M41, we need to handle that correctly in
xen.
Also drop power doamins for xen,shared gpio, xen will power up the gpio.
gpio1 is owned by M41, so we also need to check its power status in xen.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
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CM41 runs before CortexA, we should not use smmu to restrict it, because
smmu is owned by xen. Also remove MU_13/12 which is wrongly added
before.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
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change the flexspi pad settings to pull_up and drive_low to avoid
overshoot.
Signed-off-by: Han Xu <han.xu@nxp.com>
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After fix the ADMA length mismatch issue on imx8mm, we can
support eMMC CMDQ, so enable it. This patch also make imx8mm
support HS400ES mode.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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Add new dts and dtsi file for virtual i2c driver on i.MX8QXP and i.MX8QM
board.
Merge fsl-imx8qm/8qxp-mek-m4.dts to fsl-imx8qm/8qxp-mek-rpmsg.dtsi. So
delete these two files.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
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Enable RPBUS(i2c-rpmsg-imx.c) and RPMSG functions.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
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IR uses GPIO1_13 not GPIO_12 in imx8mm-evk board.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
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When system enters VLPS/VLLS mode, the IOMUXC config register
for MMDC related IO pads need to set to '0' to reduce the current
leakage for these IO pads.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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Set IR built-in on imx8 boards.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
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Enable IR on imx8mq-evk board.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
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Enable IR on imx8mm-evk board.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
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i.MX8QXP has separated irq, and shared irq for lpuart with eDMA,
it is better for uart to use separated irq although there has
no function impact.
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Update resource ID table to SCFW commit:
004247e14afc ("SCF-341 Fix bug in setting large slice clock divider")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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