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Adding the config definition for ti aic3262.
Commented by default, enable ti aic3262 and disable wm8753 to use ti codec
Change-Id: Ib03d6f1904441ac77d8906cca93410c6182ce967
Reviewed-on: http://git-master/r/57384
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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Adding i2c info needed for ti codec.
Setting dap1 to use with voice call till ti codec driver add secondary
interface support.
bug 816608
Change-Id: I391c3eb58052f8852e25c5aafe92d294316f440d
Reviewed-on: http://git-master/r/57397
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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enabling wake on wireless. Wake27 is wake event for wifi.
Bug 882822
Change-Id: Ic69e4a0f5ebc43c59bff26e4a1b6c2e5fe67de93
Reviewed-on: http://git-master/r/56191
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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It is possible for GPIO interrupt to occur when registering handler
since set_irq_chained_handler enables GPIO interrupt. Thus
all relevant variables are required to be initialized
before calling set_irq_chained_handler.
Also add initialization of interrupt status register.
Bug 884569
Change-Id: I596dfab3eb8b29722a05f06ec8c026a7b2f400b6
Reviewed-on: http://git-master/r/55612
Reviewed-by: Daehyoung Ko <dko@nvidia.com>
Tested-by: Daehyoung Ko <dko@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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This is enabled for Whislter.
Change-Id: Ic6facae8fcaf524096f01b7e136d0ee3f6209593
Reviewed-on: http://git-master/r/55971
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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---------------
ARM: tegra: whistler: BB pwr ctrl handover to user space
The Icera baseband on Enterprise is powered ON by FIL from user space.
There is no need to power ON the baseband from kernel space and it is
preferable to not do it as FIL initiates a power cycle of the baseband
anyway.
Bug 874633
Bug 875299
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ARM: tegra: whistler: change personality condition for ph450 modem
Personality check change from 0x3 to 0x2
Bug 877489
Bug 860984
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arm: tegra: ph450 power control via gpio
Bug 874633
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arm: tegra: baseband: add callback functions for null phy power off
Adding pre_phy_off and post_phy_off callback functions in null_phy_power_off
function. So that the modem handshaking GPIO is set to reflect the real phy
status.
Bug 860984
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ARM: tegra: usb: ulpi support for modem flash-less boot
- Update the null phy init sequence:
1) remove ULPI CLK tristate
2) do pinmux bypass immediately after phy reset.
3) check preinit and postinit return value
4) enable disconnect detect
- enable utmip phy
- Added pre_phy_off and post_phy_off callback functions in null_phy_power_off
function. So that the modem handshaking GPIO is set to reflect the real phy
status.
Bug 860984
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ARM: tegra: whistler: conditionally enable icera PH450 (i450) modem
- Modem related init is done conditionally depending on the board personality.
- Debug UART init is also done conditionally since UARTA shares pins with ULPI.
Bug: 877489 860984
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arm: tegra: Handler for kernel command option personality
Adding the handler to parse the kernel command option
"personality".
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kernel: tegra: whistler-baseband: Change ph450 handshaking protocol
Note that you need e450phv2 board
Bug 874633
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ARM: tegra: whistler: UARTA pinmux change
- UARTA pinx come out of SDIO pingroup.. this is for Icera flashless boot.
Change-Id: I4fba6efd455a33d1828cf48f7e0d7dc049df9d14
Reviewed-on: http://git-master/r/55755
Tested-by: Martin Chabot <mchabot@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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EMC state control register is not programmed correctly as the value
is not reset after previous write is done.
Bug 829087
Reviewed-on: http://git-master/r/40230
(cherry picked from commit 51a190b49a347968c22c1ed8187568a7ed1fb1f1)
Change-Id: Ie118594bad708cc1169b818452fdb8419e936036
Reviewed-on: http://git-master/r/55954
Reviewed-by: Liang Cheng (SW) <licheng@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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- Modem related init is done conditionally depending on the board personality.
- Debug UART init is also done conditionally since UARTA shares pins with ULPI.
bug: 877489 860984
Change-Id: Icb5ffdf67523de3db575e6002eebcd9a6aa9452e
Reviewed-on: http://git-master/r/54806
Reviewed-by: Sheshagiri Shenoy <sshenoy@nvidia.com>
Tested-by: Sheshagiri Shenoy <sshenoy@nvidia.com>
Reviewed-by: Martin Chabot <mchabot@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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remove the support to delay changing emc clock.
Bug 850852
Reviewed-on: http://git-master/r/40133
(cherry-picked from commit d17e14a17109c80575238695ac6921834d0016a2)
Change-Id: I8c482a969ab420f534fcfc9c7ad740d668e0c5a9
Reviewed-on: http://git-master/r/51130
Reviewed-by: Cheryl Jones <chjones@nvidia.com>
Tested-by: Cheryl Jones <chjones@nvidia.com>
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refactor emc code and centralize it in one place.
Bug 850852
Reviewed-on: http://git-master/r/40131
(cherry picked from commit f9de6e2cffed3d3202378aaf46438a759196565e)
Change-Id: Iccf3d195b65d4c2769c94d5cd30f4194bd1da0b5
Reviewed-on: http://git-master/r/51129
Reviewed-by: Cheryl Jones <chjones@nvidia.com>
Tested-by: Cheryl Jones <chjones@nvidia.com>
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If the screen is idle (no POST for some time), reduce the DC EMC clock
according the windows size. If external display connected, the EMC clock
will not be reduced.
BUG 828306
Reviewed-on: http://git-master/r/37106
(cherry-picked from 08bb9eed94479a37999be169c434d561d0074c49)
Change-Id: Ic9b95a5cd7255ff42254107a2a169e8514f0e63f
Reviewed-on: http://git-master/r/51128
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Adding the handler to parse the kernel command option
"personality".
bug 870313
Change-Id: Ia90e9039b77974ea1b5c5a2a1ae40badefc7c18e
Reviewed-on: http://git-master/r/53124
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
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Enabling the UAA pin group option to UARTA in personality
0x05.
bug 870313
Change-Id: I8f01a278f418826a593fcebcdda461a1080db000
Reviewed-on: http://git-master/r/53125
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
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Host modules are initialized to max rate. Not all use cases
require clocks at max rate, which increases the power consumption.
Modules from user space can request for the lower clk rate
using this ioctl.
Bug 850467
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/44579
(cherry picked from commit 621b21120db2d8894a564701637fe0a95aae6442)
Change-Id: Ib676bd3607a09cc2303980465eac2d5505bd2ded
Reviewed-on: http://git-master/r/51374
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
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Use the value calibrated by master cpu.
Bug 850933
Change-Id: If56f76f5e0e5fa47e15a9ceed4853b9e3c329552
Reviewed-on: http://git-master/r/49922
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Kamal Balagopalan <kbalagopalan@nvidia.com>
Tested-by: Kamal Balagopalan <kbalagopalan@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Change-Id: I4acfaebfd96ee357b50d7810fa18f88f0c2084c8
Reviewed-on: http://git-master/r/50185
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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bug: 856337
Change-Id: Ie50cad7f4fd42495186f119707cc87afeadab748
Reviewed-on: http://git-master/r/47205
Reviewed-by: Sheshagiri Shenoy <sshenoy@nvidia.com>
Tested-by: Cheryl Jones <chjones@nvidia.com>
Reviewed-by: Cheryl Jones <chjones@nvidia.com>
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Fix GART lockups caused by fragmentation by evicting
mapped areas from iovm space after unsuccessful array
pinning attempt.
Fix double unpin error happening during interrupted
submit.
Fix possible sleep in atomic context in iovmm code
(semaphore inside spinlock) by replacing spinlock
with mutex.
Fix race between handle_unpin and pin_handle.
bug 838579
bug 838073
bug 818058
bug 844307
Conflicts:
drivers/video/tegra/nvmap/nvmap_mru.c
Reviewed-on: http://git-master/r/38430
(cherry picked from commit 4a4cae3323d3287e77fdc504e38656974ef24848)
Change-Id: I385913569ef455a1ceb5083829959de24f5309a7
Reviewed-on: http://git-master/r/47832
Reviewed-by: Andre Sihera <asihera@nvidia.com>
Tested-by: Andre Sihera <asihera@nvidia.com>
Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Restore the target cpu frequency on exit from suspend. Also save target
frequency if set when the device is suspended.
Bug 841559
Change-Id: I98f394ef0292147c61898b5e216d859e3a26a0b5
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-on: http://git-master/r/47772
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
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This change makes tegra2_pll_clk_set_rate() will process for p field is greater
then 2. It helps to increase VCO.
Bug 852217
Bug 842032
Change-Id: I9ad1483521126a52318bd5b641cfe34e0b66ebff
Reviewed-on: http://git-master/r/47492
Reviewed-by: Bo Kim <bok@nvidia.com>
Tested-by: Bo Kim <bok@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Gabby Lee <galee@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Removed '\n' character in the input buffer to get a correct length of
data.
fixed Bug856327
Change-Id: I1a15eafa8ba3e0cc1da7872c41abc5963685cdb1
Reviewed-on: http://git-master/r/46595
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Chao Jiang <chaoj@nvidia.com>
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Added the code for arbitration lost recovery mechanism for i2c
driver and Initialize gpio number for i2c clock and data as
part of platform data.
bug 854305
This is cherry pick of change http://git-master/r/#change,43200
in main but hand-merged.
Change-Id: I2bf46cf54c04b94174435f3fb9c965b74156dd02
Reviewed-on: http://git-master/r/46288
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
Tested-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Updated i2c platform data to add i2c arb lost recovery funtion
and corresponding gpio numbers to i2c pins
bug 854305
This is cherry pick of change http://git-master/r/#change,43200
in main but hand-merged.
Change-Id: I4098a512625c16598b8596d0e46d285ca9b92d2b
Reviewed-on: http://git-master/r/47290
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
Tested-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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It may be possible that write operation on apb bus does not get
complete before disabling clock if the clock is disabled just after
the write on apb bus.
To have proper sequence of operation, it is require to read back the
apb bus to make sure the write operation is completed.
bug 833341
This is cherry pick of change http://git-master/r/#change,32556
in main but hand-merged.
Change-Id: I1d73a2fdfb35450220f53973d56984c9b89fdd27
Reviewed-on: http://git-master/r/45985
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
Tested-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
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Enabling cdev1 clk or DAP Mclk from board file instead of
codec soc file because Mclk needs to be enabled before
codec initialization. Also exposing set_parent() for cdev
clocks so that it is possible to enable them from board
file.
Bug 827709
Bug 839210
Bug 821178
Reviewed-on: http://git-master/r/37631
(cherry picked from commit 6643460bd1fa0b8cdf9ddfc75dd3dd228093819f)
Change-Id: Ie7fa948aead75c6e7e6c32a280ee336d8341ccbe
Reviewed-on: http://git-master/r/44978
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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This reverts commit a5dc52ce49d00bba963544251a1fe858e774780b.
Bug 857124
Change-Id: Ib8c350b44d8334894f96439b67a8a41acabff848
Reviewed-on: http://git-master/r/44493
Reviewed-by: Joshua Cha <joshuac@nvidia.com>
Tested-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Per the 8.4.1 section of HDMI spec version 1.4a, 100KHz is the maximum
clock rate of DDC i2c bus.
Bug 820552
Signed-off-by: Haley Teng <hteng@nvidia.com>
Reviewed-on: http://git-master/r/41490
(cherry picked from commit fba535096a0c0e3ff9ef72492ed582605aa7cd97)
Change-Id: Id7b4fe95ef623ba95e7a9df3e02162c24ee750df
Reviewed-on: http://git-master/r/44290
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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ARMv6+ architecture does not allow ioremap on system memory.
lp0 is relocated using ioremap on DRAM. If lp0 vector start address
is in system memory then use memblock_reserve and do not relocate.
Else if it is overlapping with carveout/fb then first remove the
carveout/fb using memblock_remove and then use ioremap.
Bug 827199
Change-Id: Ic602f0f2495756213face30681018529128e57b9
Reviewed-on: http://git-master/r/43685
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
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Reducing the scan timeout for the continuous polling mode
from 3sec to 2 sec to have faster suspend.
Bug 845098
Change-Id: Iec9c0cda0bc4dbe91fd683aaa9c92ef4033f1314
Reviewed-on: http://git-master/r/40222
Tested-by: Victor Ryabukhin <vryabukhin@nvidia.com>
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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In current implementation, the HSIC port cannot have PHY power off
without re-enumeration when it is suspended.
This patch will do following upon USB port suspend:
* disable the USB PHY clock
* disable the shared EMC clock
* keep the USB core but running it at 0.95v VDD
With this patch, VDD can be reduced to when the HSIC port is suspended.
There is no re-enumeration when HSIC port is resumed, also it will not
affect the normal LP0 suspend/resume.
BUG 817725
BUG 796594
(cherry picked from http://git-master/r/30224)
Change-Id: Ie0553335ae50bca1a91e94d46d14bb9127874ae4
Reviewed-on: http://git-master/r/37226
Reviewed-by: Joshua Cha <joshuac@nvidia.com>
Tested-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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3D power gate should be always disabled to keep the power. Set T20
enabled by default.
Bug 843271
Change-Id: Icf464cd107e65636440f8103ac6b104e2939e8b9
Reviewed-on: http://git-master/r/40342
Reviewed-on: http://git-master/r/43175
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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AP25 EMC scaling ladder is 23.75/63.33/95/190/380.
Device will freeze when clock rate is changed from < 95 to 380.
WAR added: Set clock rate to 190 first and then required clock rate.
Bug 821534
Change-Id: Idfd12bdba72e2918dfe0b59c5c54d02b87ec73ea
Reviewed-on: http://git-master/r/41720
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
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Protected shared bus update with bus lock - common for all shared bus
users (update procedure was already covered by individual shared users
locks, but it did not prevent concurrent access to shared rates list).
Reviewed-on: http://git-master/r/39918
(cherry picked from commit 09ca93ccf0c8400a876a23eef3cd771f2f4ac9d2)
Change-Id: Ie660fcb8c962712ceaa230a9dead684fcaf37d24
Reviewed-on: http://git-master/r/42589
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
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- handle scenarios when the number of fuses burnt
is a odd number
- wait for the fuse bock to be idle before issuing
any command
- burning of master_enb fuse is not required to be
done according to the guidelines
Bug 823552
Reviewed-on: http://git-master/r/35883
Bug 836963
Change-Id: I645da7e5ffbce10e3492c7e1bfe14be14e65b789
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/42313
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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USB PHY related charger detection logic is
implemented.
Bug 819334
Change-Id: Ica7e66509d52d787cc5c25434b45534176bc8dc7
Reviewed-on: http://git-master/r/42298
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
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Added 23.75/63.33/95 EMC scaling ladder for AP25.
Bug 821534
Change-Id: Id753369d5b3822cec400ce550c12b61581532099
Reviewed-on: http://git-master/r/41722
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
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EMC rate is specified in terms of KHz in dvfs table. In
calculation it is used after converting it to Hz i.e.
mulitplying by 1000. BUG_ON condition modified to accept
non-exact EMC frequencies in the range of 2 KHz.
Bug 821534
Change-Id: Id9c5d3fc3f6841c71155afea0ad31a696037a57f
Reviewed-on: http://git-master/r/41718
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Set the working voltage for USB to 1.1 v.
Bug 796594
(cherry picked from http://git-master/r/30219)
Change-Id: I4800c60b8aa4068d0d27e29dab43dadfb4e2d82c
Reviewed-on: http://git-master/r/37211
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Bug 836963
Change-Id: Ib4de276ae6ed1b48b90b4f6538ef1a99a21e8ab2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/42318
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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At the time of reboot, all rails need to be set to nominal to ensure
the success of subsequent boot.
bug 821969
bug 797082
Reviewed-on: http://git-master/r/30086
(cherry picked from commit 2218f77d722bdd7a6830cfccb0e7f310b7bca48c)
Change-Id: Ic853ab47e9a42ae6b549b5549af0b118ec9e00d1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/42117
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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the gpio used for vdd_fuse is powered on
by the i2c expander (GPIO_P02) present on
the pmu board.
Bug 836963
Change-Id: Ie54cd1f81f6d833757615f707bac1a4336ce8174
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/41738
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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platforms need to implement their fuse power on
functions if they do not use regulators to power
on the fuse block
Bug 836963
Change-Id: Ie70bf3c699c94a6bde90e45529bb1049e86a1461
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/41737
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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LP0 vector is allocated by BL and address is shared to kernel.
For platform with memory less than 1GB it was allocated in
the overlapping region of carveout memory. Because of it
during AVP operation it gets corrupted, which prevents resume.
Relocate AVP vector to some other location where overlapping will
not occur.
Bug 827199
Change-Id: I8ec066d8c38c34b0bd9314abe20b2e01b4a3a293
Reviewed-on: http://git-master/r/42113
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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This reverts commit 2b96783fd25eb2153cab2fb6ff92b2bacc809bed.
Recovery process is hanging because of this change.
Bug 848403
Bug 800107
Change-Id: I1b7d3f6c08d6db40eda077e5f128c4bf3be681ac
Reviewed-on: http://git-master/r/41818
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Kaushik Sen <ksen@nvidia.com>
Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com>
Tested-by: Joseph Lehrer <jlehrer@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
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CTS File permission test expects there shouldn't be any writable
permission for Group and Others for any file in kernel.
Bug 840409
Change-Id: Ia31aa02e9e49840823ec080ab7d42c2c197f0602
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/41540
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Manoj Gangwal <mgangwal@nvidia.com>
Tested-by: Manoj Gangwal <mgangwal@nvidia.com>
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Required to pass android.net.cts tests.
Bug 789868
Change-Id: Ie43c02b4c4b03d929744678c399bbad980658ed3
Reviewed-on: http://git-master/r/41234
Reviewed-by: Rahul Bansal <rbansal@nvidia.com>
Tested-by: Rahul Bansal <rbansal@nvidia.com>
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Change-Id: I115ab2464378df094dae67268c919980bd72b843
Reviewed-on: http://git-master/r/39785
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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fb_mmap maps current window so that content of screen is
accessible through mmap sys call to user space components.
BUG 832288
Change-Id: I10ccb0b70c951f6d43dbd8a7a1e59e86c0ee75e9
Reviewed-on: http://git-master/r/39204
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
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bug: 842809
Change-Id: I68f8a4c358c490c0b66ee55f49de460aced50139
Reviewed-on: http://git-master/r/40096
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
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some users might enter fuse data starting
with 0x/x. this will mess up the fuse programming.
do not consider 0x/x while programming the fuses.
also fix some compilation warnings
Reviewed-on: http://git-master/r/#change,38933
(cherry picked from commit fc8e1e492ac362a44ea6254759431d8f1fb1695c)
Bug 836963
Change-Id: If0503d4e22479e2ce230d53f538eea16d39817df
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/39614
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
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