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1. Pull in secure memory support from 3.0.35 kernel.
2. Pull in SECVIO support from 3.0.35 kernel.
3. Make changes to support device tree.
4. Add device tree setting for SECVIO sources.
[<vicki.milhoan@freescale.com>: Edited to apply to 3.14]
Signed-off-by: Dan Douglass <b41520@freescale.com>
(cherry picked from commit f3bfd42e2db3af8326734bebf750e94e74734f6e)
Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
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Add support for CAAM job rings, Secure Memory, and SNVS
to the i.MX6SX device tree.
Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
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Enable OTG and host 1 USB function.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Li Jun <jun.li@freescale.com>
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imx6q-sabresd-uart.dts.
Silex UART BT is using GPIO1_2 as the reset, which is in conflict with
the one used by charging LEDS.
Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com>
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based on imx_3.14 kernel, add mcc pingpong and tty tests
on imx6sx sdb and ai boards.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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The platform related codes changes when enable mcc2.0
on imx_3.14 kernel, and tested on imx6sx sdb board.
- keep imx6sx soc related apis in mcc_imx6sx.c/h
- keep linux os related apis in mcc_linux.c/h
- add some new mcc callback in mu driver, since the
gie3 of mu is used as cpu2cpu interrupter in the mcc
implementation on imx6sx.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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set the dual bsd/gpl copyright of the mcc common codes
implemented in linux bsp release.
add 2015.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
(cherry picked from commit d7f8c4eff50ba78b82484597bd301c4a87dfe082)
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Common codes changes in the mcc 2.0 updates
- common definitions are moved from mcc_config.h to mcc_common.h
because that these definitions are common for the standalone mcc
stack, and shared by different platforms, such as Linux, MQX.
- re-define the common api _psp_core_num(), and _psp_node_num().
Let them to be no platform dependency.
- move the definition of the MCC_OS_USED in mcc_config.h
- new add on mcc_config_linux.h file, contained the platform
related macro definitions contained in mcc_config.h before.
- add the related linux modifications into mcc_api.c/mcc_common.c
when implement the mcc2.0 into linux BSP.
- fix one potential bug that all the share memory operations should
be protected by sema4.
Acked-by: Shawn Guo
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
(cherry picked from commit 541325a16b6db73a86a5a86049145b0060805c7c)
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This is the base line of the mcc version 2.0.
Acked-by: Shawn Guo
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
(cherry picked from commit cfd44c266e3b8a833ac624b86be627efbda6aaa9)
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There is one BUG(TKT238285) in ecspi module in DMA mode,but
it only found on i.mx6dl now, so enable dma support on all
i.mx6 chips except i.mx6dl
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit fa9ef1796819aadbb1ea184613d4fdd3de1b46c6)
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esai_ipg clock's parent is ahb, not ipg.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Implement busfreq notifier calls used when busfreq entering low_bus_freq_mode.
When the system lower the bus frequency, some modules can be affected by bus
frequency change. Adding notifier call chains that allow driver affected by bus
frequency can be notified before and after low_bus_freq_mode.
Signed-off-by: Bai Ping <b51503@freescale.com>
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On i.MX6SL, we must make sure ARM:IPG clock ratio is within 12:5 when entering
wait mode. If the system is in low_bus_freq_mode, the IPG is at 12MHz
according the busfreq code. So the max rate of ARM is 28.8MHz when entering
wait mode. As there is no way run at this clk rate, so set ARM to run from
24MHz OSC.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Before changing the arm_podf, the pll1 must be output enabled according
to the hardware design.
Refer to the clk tree implementation code for i.MX6SL. pll1's output will
be disabled when no clk is sourced from it. In busfreq code, in order to
successfully change the arm_clk rate, we must make sure pll1's output is
enabled before changing this clk rate. add imx6sl_enable_pll_arm() calls
to fulfill this requirement.
Additionally, only a bypassed output clk is ok, so no need to make sure pll1
is powered up.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Add a space between KERN_DEBUG and the debug message string.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Enable low power idle for imx6sl. When the busfreq is either
in ultra_low_bus_freq mode or audio_bus_freq_mode, we Can save
more power by reducing the system frequency further in ldle.
At present, Only two idle(WFI and WAIT) are supported.
WFI --> normal ARM ilde (first level idle)
WAIT mode --> low power idle (second level idle)
When entered WAIT mode, change the DDR, AHB/AXI and ARM clk frequency
as below if the system is in:
1. ultra_low_bus_freq:
DDR freq to 1MHz,
AHB/AXI freq to 3MHz,
ARM freq to 3MHz.
2. audio_low_bus_mode:
DDR freq to 25Hz,
AHB freq to 8MHz,
ARM freq to 8MHz.
Anatop can be put in low power mode when all the PLLs are powered down.
We can enable the low power bandgap and disable the rugulator bandgap,
enable the weak 2p5 LDO and disable the 2p5 LDO.
Signed-off-by: Bai Ping <b51503@freescale.com>
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For the QSPI byte address not aligned in ROM code and kernel, we have to reset
power cycle to workaroud this issue. Use WDOG_B pin to trigger PWRON of pfuze.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 86f82eadc612a746ab57760f78754e0619aa48b1)
(cherry picked from commit 9b85071287145bf16e8202c2be4fdf7a076f7f0d)
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QSPI-NOR reboot failed in case of larger flash size such as 256M used, because
kernel QSPI-NOR flash use 4-bytes-address mode to visit 16MB+ area but ROM code
use 3-bytes-address mode to access QSPI-NOR. Thus, we have to use WDOG_B to
reset QSPI-NOR flash to workaround this.
Note:
Please update the u-boot with the below u-boot patch, otherwise system will
reboot endless while kernel boot:
"MLK-9819: ARM: mx6sx: clear WDOG3 Power Down Enable bit for i.mx6sx"
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 89b88be2a870124d58080970b37f93d868093e9a)
(cherry picked from commit d86a750522b354537f91a4403e349849c5dfcf3d)
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Support ldo-bypass mode on imx6sx-17x17/19x19 and imx6sx-sdb-reva board.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Support ldo-bypass mode on imx6sx-sdb revb board by default and
add ldo-enable dts file.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Add reva board dts file since we use revb board as the default dts file.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Add imx6sx-sdb baord uart5 DTE pad set. To avoid a flood of dts files,
there only comment out DTE pinctrl set. If user want to test DTE mode,
it needs to rebuild the DTB file.
(Cherry-picked and merged from commit 4bd6e1654495e190e61a70c9b2c44fda931e2727)
Signed-off-by: Fugang Duan <B38611@freescale.com>
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i.MX6q/dl, i.MX6SX SOCs enet support sleep mode that magic packet can
wake up system in suspend status. For different SOCs, there have some
SOC specifical GPR register to set sleep on/off mode. So add these to
callback function for driver.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add FEC magic-packet feature support.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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syscon shouldn't be added into gpc dts, otherwise, the gpu
wound't be powered on properly.
remove this commit.
This reverts commit 77ddc73cc9504576942d77813abe559b44f59123.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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The orignal regulat num of the MPCIE_3V3 regulator is wrong,
change it to the correct one.
Otherwise, there would be the following warning when boot kernel.
WARNING: CPU: 0 PID: 1 at fs/sysfs/dir.c:52 sysfs_warn_dup+0x6c/0x8c()
sysfs: cannot create duplicate filename
'/devices/soc0/regulators.18/3.regulato'
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.14.24-01139-g690bd11 #166
[<80014e6c>] (unwind_backtrace) from [<800118ac>] (show_stack+0x10/0x14)
[<800118ac>] (show_stack) from [<806b0018>] (dump_stack+0x78/0xc0)
[<806b0018>] (dump_stack) from [<8002c1ec>]
(warn_slowpath_common+0x68/0x8c) [<8002c1ec>] (warn_slowpath_common)
from [<8002c240>] (warn_slowpath_fmt+0x30/0) [<8002c240>]
(warn_slowpath_fmt) from [<8012de80>] (sysfs_warn_dup+0x6c/0x8c)
[<8012de80>] (sysfs_warn_dup) from [<8012df28>]
(sysfs_create_dir_ns+0x88/0x98) [<8012df28>] (sysfs_create_dir_ns) from
[<80274be8>] (kobject_add_internal+0x9c) [<80274be8>]
(kobject_add_internal) from [<80274fe0>] (kobject_add+0x4c/0x98)
[<80274fe0>] (kobject_add) from [<80317bf0>] (device_add+0xe0/0x51c)
[<80317bf0>] (device_add) from [<804e2dd4>]
(of_platform_device_create_pdata+0x)
[<804e2dd4>] (of_platform_device_create_pdata) from [<804e2edc>]
(of_platform_b) [<804e2edc>] (of_platform_bus_create) from [<804e2f38>]
(of_platform_bus_create) [<804e2f38>] (of_platform_bus_create) from
[<804e3090>] (of_platform_populate+0) [<804e3090>]
(of_platform_populate) from [<80cf2d40>] (imx6sx_init_machine+0x38)
[<80cf2d40>] (imx6sx_init_machine) from [<80cde264>]
(customize_machine+0x1c/0x) [<80cde264>] (customize_machine) from
[<800088cc>] (do_one_initcall+0xe8/0x144) [<800088cc>] (do_one_initcall)
from [<80cdbc04>] (kernel_init_freeable+0x104/0x) [<80cdbc04>]
(kernel_init_freeable) from [<806abfb4>] (kernel_init+0x8/0xec)
[<806abfb4>] (kernel_init) from [<8000e5f8>] (ret_from_fork+0x14/0x3c)
---[ end trace f90dcd76c3b24ac8 ]---
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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Disable ethernet phy AR8031 EEE mode in default to reduce the IEEE1588
latency.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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By doing this, we can allow SDMA driver to allocate its memory from iram
when using i.MX6 SoloLite SoC.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
(cherry picked from commit aa527b38d52af233641edc500acae0e6212ccdb3)
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Add property "revision-a10" to device tree to set the default command
set to A10.
Signed-off-by: Zidan Wang <b50113@freescale.com>
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SAI and SAI_IPG are controlled by the same clock gating bits, so register
them with imx_clk_gate2_shared.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 1223c730e5ca58794721c26b3803b96f95fd3937)
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SSI and SSI_IPG are clocks controlled by the same clock gating field, so
register them with imx_clk_gate2_shared.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
(cherry picked from commit 42222ee66ae046187b0ca8ec4b0c00c8832810a7)
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- enable pcie on imx6qdl sabreauto boards.
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
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Enable pcie on imx6sx sdb board.
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
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- imx6sx pcie phy has its own power regulator. Add the
pcie phy power suppy into im6sx pcie dts and binding.
- in order to align with imx6qdl's pcie dts, re-format
imx6sx pcie dts.
- in order to align with imx6qdl pcie dts format and
keep clean of imx6 pcie driver, keep the pcie phy clock
in imx6sx pcie dts, although it's the parent clk of the
pcie bus clock now, and would be enabled automatically
when pcie bus clock is enabled. secondly, it's
possible that the external osc maybe used as source
of the pcie_bus clk in board design in future.
- disp_axi clock is required by pcie inbound axi port.
Add one more clock named pcie_inbound_axi for imx6sx pcie.
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
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In order to manipulate gpc bits for imx6sx
pcie in driver, add syscon into gpc dts
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
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When the busfreq is in audio_bus_freq_mode, the AHB bus is at 8MHz,
in low_bus_freq_mode, the AHB needs to run at 24MHz. So when switching
from audio_bus_freq_mode to low_bus_freq_mode, make sure the AHB is at
24MHz in low_bus_freq_mode.
Signed-off-by: Bai Ping <b51503@freescale.com>
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enable CONFIG_IMX_SEMA4 by default for imx_v7_mfg_defconfig.
Signed-off-by: Anson Huang <b20788@freescale.com>
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this patch adds A9-M4 power management, including
below features:
1. busfreq: M4 is registered as a high speed device
of A9, when M4 is running at high speed, busfreq
will NOT enter low bus mode, when M4 is entering
its low power idle, A9 will be able to enter low
bus mode according to its state machine;
2. low power idle: only when M4 is in its low power
idle, busfreq is staying at low bus mode, low
power idle is available for kernel;
3. suspend: when M4 is NOT in its low power idle,
when linux is about to suspend, it will only
force SOC enter WAIT mode, only when M4 is in
its low power idle in TCM, linux suspend can
enter DSM mode. M4 can request/release wakeup
source via MU to A9.
as M4 can NOT switch its clk parent due to glitch MUX,
to handle this case, A9 will help switch M4's clk
parent, the flow is as below:
M4:
1. enter low power idle, send bus use count-- to A9;
2. enter wfi and only wait for MU interrupt;
3. receive A9's clk switch ready message, go into low
power idle;
4. receive interrupt to exit low power idle, send request
to A9 for increase busfreq and M4 freq, enter wfi
and only wait for MU interrupt;
5. receive A9 ready message, go out of low power idle.
A9:
1. when receive M4's message of entering low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to OSC, ungate M4 clk,
send ready command to wake up M4 into low power idle;
2. when receive M4's message of exiting low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to origin high clk,
ungate M4 clk, send ready command to wake up M4
to exit low power idle;
Signed-off-by: Anson Huang <b20788@freescale.com>
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As A9 and M4 share many resources on i.MX6SX, especially for
clk and power related resource, so we need to handle the hardware
conflict between these two cores, there are two cases that we
need to consider currently:
clk management: for every clk node, only when both A9 and
M4 do NOT need it, then we can disable it from hardware;
Here we use MU and hardware SEMA4 to achieve our goal, MU is
for communiation between A9 and M4, SEMA4 is to protect the
shared memory.
For clk management, we use shared memory to maintain the clk
status for both A9 and M4 side, and this shared memory is
protected by hardware SEMA4, A9 and M4 will maintain their
own clk tree info in their SW environment, and get other
CORE's clk tree info from shared memory to decide whether
to perform a hardware setting change when they plan to.
Signed-off-by: Anson Huang <b20788@freescale.com>
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When resume from DSM with Mega/Fast off, we need to restore
the right QSPI module for M4, so get the qspi index from dtb file.
Signed-off-by: Anson Huang <b20788@freescale.com>
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As M4 is executing on QSPI2 flash, and QSPI is inside Mega/Fast
domain which may lost power in DSM, so we need to do save/restore
of QSPI2 controller to make sure QSPI flash can be accessed before
waking up M4 after exiting from DSM.
Signed-off-by: Allen Xu <b45815@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
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add MU driver support in mach-imx, all the MU functions
and communications between A9 and M4 will be done in
this file, including MCC, shared clk/power management.
Signed-off-by: Anson Huang <b20788@freescale.com>
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add MU support for i.MX6SX.
Signed-off-by: Anson Huang <b20788@freescale.com>
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1. add i.MX6SX SabreAuto board M4 dts support;
2. add shared memory node support for AMP clk/power management;
3. add qspi restore node for suspend/resume with Mega/Fast off
when M4 is enabled and running on QSPI flash.
Signed-off-by: Anson Huang <b20788@freescale.com>
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add SEMA4 support for i.MX6SX.
Signed-off-by: Anson Huang <b20788@freescale.com>
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enable CONFIG_IMX_SEMA4 by default.
Signed-off-by: Anson Huang <b20788@freescale.com>
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add HAVE_IMX_AMP and select by default for i.MX6SX.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Enable OV5640, VADC and CSI driver in imx6sx AI board
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Enable OV5640, VADC and CSI driver in imx6sx SDB board
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Disable netfilter feature for enet can increase 30Mbps bandwidth
for imx6sx enet tx path.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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