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Conflicts:
arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/board-ventana.c
drivers/misc/Kconfig
drivers/video/tegra/dc/hdmi.c
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
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Enable profiling support by default in Tegra kernels, to facilitate
usage of tools such as Perf and OProfile.
Bug 899639
Change-Id: Idf346136ca618bd2a23e549792948f287e0045aa
Signed-off-by: Ryan V. Bissell <rbissell@nvidia.com>
Reviewed-on: http://git-master/r/66231
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R3180797dbbd70066989ed536d79a4a53dae0ce25
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Bug 904530
Change-Id: Iee764eea7f4e4c22a9f333bace77ce2fddf57afc
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/66830
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: Red1e9abfa5352de3e292a66ec3c1a8ed68ec779f
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bugid 844268
Use correct regulator current value obtained from bootloader
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Change-Id: I9059a5e83c88c6fc0e933acd3c4ab6e6b9c35078
Reviewed-on: http://git-master/r/67025
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Rebase-Id: Rce035e804a189df47a5b5c2a03f418d88cd9147a
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configuring wf_wakeup gpio
Bug 907141
Change-Id: I799421d640c25151edcb6a2bb72f941cd4ce1c2a
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: http://git-master/r/66890
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>
Rebase-Id: R8325d47e49ea11988f42251fa75211e6c129315a
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1) Enabling ULPI CLK after MDM2AP_ACK is asserted
2) Driving linestate by GPIO before removing the ULPI data tristate
Bug 889484
Reviewed-on: http://git-master/r/60104
(cherry picked from commit 795b9ddcedf3f6465c6a352005c8d8615a36e739)
Change-Id: Idde92fec46cdb26bc336ffd2d12a2cfb65b3f2e9
Reviewed-on: http://git-master/r/66995
Reviewed-by: Steve Lin <stlin@nvidia.com>
Tested-by: Steve Lin <stlin@nvidia.com>
Rebase-Id: Re67fcacdd2b3efcbd99e9861fb6bc5e3a2f204aa
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Updated Tegra3 xL core speedo and nominal voltage settings.
Re-factored nominal voltage selection, since new data introduced
dependency of core voltage on both CPU and core speedo id.
Bug 841336
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 3330ce743434866502fd6b33d7d1718ec4ab4675)
(cherry picked from commit a9fb4cbc865e78706c72186ebac286506cd5b301)
Change-Id: I244df08153a6a275a2fe331c72e03d03f18a8ea1
Reviewed-on: http://git-master/r/67014
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: Rd35cb9ac1fbcb424548e05d10d5622744394e796
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Bug 841336
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 92a342487a7bfe68d3c3366bbcd74c44a59f94d6)
(cherry picked from commit 5f0a23567f1acfd07325f324d41cea50eab84d80)
Change-Id: I793e427c7f738722786c6dd3d29411c75be50f93
Reviewed-on: http://git-master/r/67013
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R7e187fc24adac12f7a91790b74102578ed320e89
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Added minimum voltage field to Tegra3 EMC frequency scaling table.
Adjusted default (common) EMC DVFS mapping, respectively, when EMC
frequency table for the particular board/dram chip combination is
loaded.
Bug 895245
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 1fe4d12c4abdd08abd45eb755d3d50780cafb19c)
(cherry picked from commit 4020c6aacfd5ec3c7106cc05e720bc4c356ac58d)
Change-Id: Ia10183001996aee37259efdb533640ebf72d552a
Reviewed-on: http://git-master/r/67012
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: Rb1cb3a849c9c870b0c338a5a0a7e9cb9a7572674
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- Doubled PLLC (cbus parent) rate to make sure that cbus clients always
have only even dividers.
- Added new shared bus user mode - SHARED_AUTO for user (like Host1x)
that just follow the bus, but by itself does not require bus rate
above the minimum.
Bug 895245
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit e95329c67d4efc424d3408b363e092c02c066ef7)
(cherry picked from commit 773e089f2ab676e9ea8afd7aaa0458654a3772d9)
Change-Id: Ie1488f38e3cb948d69738c2eef4ae9cd7ae0b47d
Reviewed-on: http://git-master/r/67011
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: Rdd00a21fc2f58efdfeec5733c0307627da1fb430
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Bug 865305
Change-Id: I1e300db033a22935bcc0cd6c24f8d9d3460b3475
Reviewed-on: http://git-master/r/66120
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R54cebc69c16bbedb4ed2dbf3fc33dbc34456cb57
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Bug 865305
Change-Id: I4dc602d84e9a0037b8078ccacee59d78caa5dc2a
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/66118
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R6504de46ef65a4b5bb154d668a8e21d01fc438a5
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Debug output of nvhost needs nvmap_handle_ref. This patch exposes it as part
of the public API.
Change-Id: I8d12083cb9ac43291c457d6a262029d00e106c9a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/66071
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: Rbe38a80af896cdb59e37efdfadd520405790886c
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To get correct xdpi/ydpi information in android framework,
we should add LCD physical size information in mm unit to
dc out structure.
Bug 903247
Change-Id: I497256a423c78f976b4e0bfdda94422cf900286a
Reviewed-on: http://git-master/r/66023
Tested-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Re22637cdb581d7cc9abdb6f1ce1c5969e8b8c240
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Renamed client driver for nor clock from "nor" to
"tegra-nor".
Add NOR flash aperature as valid address range in
ioremap.
Reviewed-on: http://git-master/r/44746
(cherry picked from commit 151b678580c43fa53bacd22f7f3d847d3eac3f6d)
Change-Id: I61bcb316f3e9f757f24260bc24e2c4378f8e3326
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/66706
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Rebase-Id: R2e2a9a1ee7162a8073758150e56d5c1f8aa1f2fd
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Added NOR platform device for Tegra.
Reviewed-on: http://git-master/r/56895
(cherry picked from commit 6b93835cef6321f286b8efcd032a1a1cc7a6ae9d)
Change-Id: Ie0219f1b7534f140a1da924f4f97a52f50d59ad2
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/66705
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: R8ca0f2697a54ee48996c57af936bcc69c942db46
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Corrected the range check for enabling gpio for TSP62361B because
tegra_gpio_enable() is for tegra gpio only
Bug 897387
Reviewed-on: http://git-master/r/65123
(cherry picked from commit f7ef3d5a8a56a5050174383da1818c80a65729bd)
Change-Id: I66e08170596678a267f25602f0daf79a3e0d34bd
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/66609
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R14092c5f0f254e11358349e9ecfc84faa0228cb8
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Bug 882012
Bug 866726
Bug 896181
Bug 894789
Bug 861828
Bug 852480
Bug 872156
Change-Id: Ib87ca49d2b5c7e865571d79a37a5739e92d2cdf6
Reviewed-on: http://git-master/r/66055
Reviewed-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Tested-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Ra9d5d0c801460e62d74066e415f6a9459feb8967
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PM313 SKU0001 supports selecting BPP ( 18bpp or 24bpp )
Bug 822980
Reviewed-on: http://git-master/r/61005
(cherry picked from commit c6f9f5ebfe5f85bc56298092dce142980bed5d71)
Change-Id: Ifa25704d91bdd9de164b2baac835c38f0cdc0813
Reviewed-on: http://git-master/r/66576
Reviewed-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Tested-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Rebase-Id: Ra8e388176b4d7d35915809d5272524ad0fa02cae
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Fix compiler warning when PM_SLEEP and HOTPLUG_CPU are not configured.
Change-Id: I6e9e7aaf9c63752d0c33363b1cced75b4437d82d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/66508
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Rebase-Id: R5687b9e034e004907ba01263948bf839544adb1b
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Set MC arbiter limits before EMC clock change on Tegra3.
Bug 896654
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 16f545012457a04ba38f4f8bf80646b18a74cb2f)
(cherry picked from commit bd29cb18f1d26cc3a0fdc8933a08158d623fed58)
Change-Id: I080f21030007909bece5272ccdb93f8a85d4b13b
Reviewed-on: http://git-master/r/66515
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R0561570b37cdff800f0a7f71558eef16eb82cc59
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Bug 841336
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit d98da0dcb175787a6c6a26c87b6f5ad84ab3da8b)
(cherry picked from commit 865746e6c5938db1d7517eca916033ee13e2d290)
Change-Id: Ie26a1ccafcf8455a9d4d93d0d4e2fc330f5162f6
Reviewed-on: http://git-master/r/66514
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R8a5f24043e5fdd79cc927ef55f3ea031f093124f
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Bug 841336
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 459a539b413bc34fa6bed54cc363b4a6ffbaff59)
(cherry picked from commit 470c3c4fad40a570dedfd51a52577fd4c91c5269)
Change-Id: I63214eaa437345bf7657f4c53a6dd73473e1e532
Reviewed-on: http://git-master/r/66513
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R9e3e92e6c27da3c8760b01cda223463c75d6d16f
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Added configuration option TEGRA_PLLM_RESTRICTED - when enabled,
PLLM - memory PLL - usage may be restricted to modules with dividers
capable of dividing maximum PLLM frequency at minimum voltage. When
disabled, PLLM is available as a clock source with no restrictions
(current configuration), which may effectively increase lower limit
for core voltage if high grade SDRAM is used.
Implemented PLLM restrictions in Tegra3 clock framework and DVFS, but
keep them disabled by default.
Bug 884419
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 5313ebcae92839146870d5865bc0f4cd08b35c61)
(cherry picked from commit 634647a9d2a8c1e03c8d98d0b2199950c947acc3)
Change-Id: I012452d92830ad6b63ec407350568b8c316b3caa
Reviewed-on: http://git-master/r/66512
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R22de0f09e7af2640499ec8cd96e974328d78bace
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Introduced kernel config variable to enable internal tsensor
EDP and throttling support feature -
CONFIG_TEGRA_INTERNAL_TSENSOR_EDP_SUPPORT
bug 848755
Reviewed-on: http://git-master/r/53822
(cherry picked from commit bacc6c8c7fc150db8d678281fd9cd1536d18d2bb)
Reviewed-on: http://git-master/r/65451
(cherry picked from commit 2793d55e3d50bb8d76e1191f8a0f53f822fbd875)
Change-Id: Ia15d13e670192b6656f20f29b5348aa995d95749
Reviewed-on: http://git-master/r/66444
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R3ed1f0cbdd9bc1ba52b7d37930df4ab2d81e6598
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bugid 844268
Reviewed-on: http://git-master/r/65547
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 72d41cc5200454175d8dc04c761c983405e4d901)
Change-Id: Ica5aaf0bedb02bff3485cdcb76e81da80896a309
Reviewed-on: http://git-master/r/66520
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Rebase-Id: R7ed6a74e13a6900490c83a15f5adc00c5163d663
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Enabling the shutdown from the pin SHUTDB.
bug 900732
Reviewed-on: http://git-master/r/65442
(cherry picked from commit fa523f222c1db34a0e11f433bde3e0f5e8c408f3)
Change-Id: I7c2cdce58b830cff367c7cdc365f792785c07650
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/66326
Rebase-Id: R96ac32c68865680dc2b0448f918f4f60490709ba
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The mask used to check bit EMEM_NUMDEV in register EMC_ADR_CFG is
wrong for T30. Correct it.
Change-Id: I3deb1229cb27081049de1a4f2fd69e21507fa853
Reviewed-on: http://git-master/r/65927
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R328e76d0f107d1b2fe1f27a81c1fab82dc4808d6
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Registering the tegra based keyboard driver.
bug 887629
Change-Id: I6908052eaa0efcaedb6bf101374f3e6598c8722f
Reviewed-on: http://git-master/r/65859
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R4bc41ee23fcbdd8c4320326884a88e3e245349e1
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Powering off the cardhu if onkey is pressed for longer time
(more than 5 sec).
The short key (< 1 second) takes system into suspend,
the key press to 1 to 5 sec popup shutdown menu and more than
5 second power off the system.
bug 810512
Reviewed-on: http://git-master/r/65108
(cherry picked from commit 71ecd268ab0a3fb8417c1d9a13dcb5e06fc3ac7a)
Change-Id: I1da27b2464445131ae82bc67a419d064c8149d60
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/65805
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R7f958a5d99de7dc354d807acd75bc319cfe87b30
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Turns on phase_in_adjustments on for Cardhu / Enterprise and
updates flicker control
Reviewed-on: http://git-master/r/64522
(cherry picked from commit 9b217486322c4da8ba0df0ec6710caf94efbd721)
Change-Id: I1fc4ef0b04881c9f2b34b0ab2c88d6b97c88815c
Reviewed-on: http://git-master/r/65626
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R1e8eb79e658556337666186e416f7fccc5a4508b
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phase_in_video (renamed) phase_in_adjustments
-Backlight and pixel adjustments
step linearly every ADJ_PHASE_STEP frame updates
phase_in (renamed) phase_in_settings
-Enable/Disable + Agg changes are phased in
Reviewed-on: http://git-master/r/64521
(cherry picked from commit 7d8e34986ba49cf3586a155bdf5a6ae8b02639a9)
Change-Id: Iaf0c1773ce440d93ecd76beaa877891b47652510
Reviewed-on: http://git-master/r/65619
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rd2243cc65151f4bf6a4dc189e52b10e8a7afd389
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bugid 897071
Reviewed-on: http://git-master/r/63432
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit c37d623192e6c07950c711eb9cbc584813567cd7)
Change-Id: Id7faa07f9b7ccc779557a79bb704b901fd67436e
Reviewed-on: http://git-master/r/65289
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rb62dd30fc38085b89f5921c87e4115472221c622
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Bug 902803
Change-Id: Ifcdac4fc50ef0dde563db1bcbbf7ebd9d3b589ce
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/65262
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R0101ed7fead838b1259afd05f2e6ef648b70a678
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GPIO based lp0 wakeup needed to support search for its irq
as well as GPIO bank irq in table. This is implemented
in this change.
lp0 wakeup irq enable using enable_irq_wake needs to be
called in specific drivers. Additionally, in some cases
wake irq needs to be updated in tegra wakeup table.
bug 890309
bug 902114
Change-Id: I983318172ffb020f565763cfe2bb29018223dcd0
Reviewed-on: http://git-master/r/64395
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rffcadeee341a73f2ea6d62e31d507e9a8dce5a0e
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Bug 902303
Change-Id: Ib9d9e03a7879ee51a84d22d7cc571addd376b548
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/64181
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R80dff3a7bf0c9b16b41c47d9f2d36f90030fb2d1
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Bug 901430
Bug 905813
Change-Id: Id57f870262eebe6a2017b808d1a66624f903989d
Reviewed-on: http://git-master/r/64103
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rc3cad5fafa9e62fa10099bc4dc1281954a04b8f5
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Adding battery present support to fuel-gauge driver
so as not to report battery charecterstics when
battery is not present
bug 873965
Reviewed-on: http://git-master/r/61831
(cherry picked from commit f7087f71f5ed04d5a6c88fa6c8296f85029e2efd)
Change-Id: I3cf95d530845388d189ef860ba4ee7d933dd3fd8
Reviewed-on: http://git-master/r/64091
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rdaf381deafc9f549522779d7e3baad21f3cd7834
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Enable RTC_DRV_TPS6591x for tegra3,
and disable RTC_DRV_TEGRA, which is for internal rtc.
BUG=889820
Change-Id: I0e6aa1947f466c5e364c948305a18eb3d8f09560
Signed-off-by: Wei Ni <wni@nvidia.com>
Reviewed-on: http://git-master/r/58935
Reviewed-by: Peer Chen <pchen@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-on: http://git-master/r/63246
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R5184292bf63f40c99b929799f9dd36dbadfaddd0
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The L2 cache RAM is preserved over LP2 so omit the L2 cache flush
in tegra_idle_lp2_last().
Bug 880338
Change-Id: I6aa30c712b6e467bd48e9c1959da2a69453a8f43
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/59892
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R6eee47d009d45d0e20254a97df919bf2fc34e6cd
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To quickly enable mobile sanity, we had previously turned this option
to '=y', but just removing the config option should be sufficient.
This change removes the CONFIG_USB_NET_AX8817X from the def_config files.
bug 881005
Change-Id: I40b2ccc8e50165c1f2d526cb4ef3770f03283e50
Signed-off-by: Matt Pedro <mapedro@nvidia.com>
Reviewed-on: http://git-master/r/65231
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R2bab65d06a2ef282adf5757b49565eda6329450f
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Returned error code from Tegra3 shared_bus_set_rate().
(cherry picked from commit b9aea1656af4d3e17433c82611fe5e7146a41733)
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 92cd5c809536e4c7c8a30b08d033346bb4f147a3)
Change-Id: Iaa1c93e2303f0d4e6dd35f00bbd7010e3ef90a3f
Reviewed-on: http://git-master/r/64768
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: Rbb19019bca965394d433cf16142e8b51c80b7af0
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Record dvfs client voltage rate request only after over-voltage error
is checked (otherwise, after over-voltage error rail goes above the
limit when another client requests voltage change).
(cherry picked from commit 9151f77b545dc5b898ad16ceb695cc57764f94e0)
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 40243988e73a13a5c94db410cb0335fa8a9b1e42)
Change-Id: I70769b2ffd7303db6e54bfc3e07b47ea3e67b7b8
Reviewed-on: http://git-master/r/64767
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: Re82214f06084d58eed67edb35443f7a72ac4d112
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Add Tegra3 emergency throttling API to directly control G-CPU super
clock skipper underneath clock framework, dvfs, and cpufreq driver
s/w layers. To be used by system power supply over-current ISR.
(cherry picked from commit fca2a12e90684526b2b7aeeb3af31de4254ad939)
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit b30bf0b313131037baffed7b6467eb1e0f021d19)
Change-Id: Ice064326d46f868a9d59d2e1f53930d644fdfc02
Reviewed-on: http://git-master/r/64766
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: Rf42ae930ba90de1c40843b5565251e4c1c92a642
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WM8753 spkr_en gpio entry was added mistakenly. Whistler-WM8753 audio
module does not have any gpio for enabling speaker.
Bug 872652
Change-Id: I4c5032f0b9224275ba4f4b4aba5b94e80ec7f99d
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/66092
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Rebase-Id: R1c3602f38712e8d3d43c1175f06596e4e2d2eece
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This reverts commit 5e143436d04465c937c1a242808a99c46393af3e.
gdbserver has READ_IMPLIES_EXEC bit set, which propagtes to the
exec under debug. This results in application failing to run in
some cases. Revert the change to address this issue.
bug 894472
Change-Id: I9f856f50c94e61ac59beaf9c8f257899d1964d86
Reviewed-on: http://git-master/r/65550
Reviewed-by: Antoine Chauveau <achauveau@nvidia.com>
Tested-by: Liang Cheng (SW) <licheng@nvidia.com>
Reviewed-by: Simo Melenius <smelenius@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R9f68ba30084adbc2b5d6818eed2ee8ce2baffe69
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Based on characterization, at high temperatures Tegra will
draw more than 1mA, which is what the datasheet reports for
the low-power mode of LDO4.
So removing the LOW_POWER mode flag which makes LDO4 in low
power mode in suspend.
bug 890770
Reviewed-on: http://git-master/r/64825
(cherry picked from commit f4263c693e235c52d7ad4ad32d2508b4a6393508)
Change-Id: I9289a504af71fa488d30d77aa6cbb6e1d7dd05a4
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/65456
Rebase-Id: R3cf4b2dfa2b5fea9fe281cad769fb5addc241abd
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- Moved validation of EMC maximum rate against nominal core voltage
from common dvfs initialization to board specific EMC scaling table
setup (a logical place to do it, since EMC DVFS is board dependent)
- Used current rate as rounded EMC rate if no EMC scaling table is
provided (instead of maximum EMC rate - no sense in attempt to set
maximum rate, or any rate, for that matter, if there is no table).
- Cleaned EMC initialization procedure
(cherry picked from commit 4f655077e09c0dc4abc50d190d82c91473e2e81c)
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit a213668b4f54b8ea7603a6d1e71f8b4ab1998bf7)
Change-Id: Id61f33e42556a6415e45b014bcadace600dd86d5
Reviewed-on: http://git-master/r/64765
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R697e04b6140eb0084bdb341febe3acdf91d93535
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bugid 844268
Reviewed-on: http://git-master/r/64185
(cherry picked from commit a27e20a84ce1bab8a1d37f12f7f9260d9d32dbfe)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Change-Id: I88b108fd44719828e11499606ab7ef754f76ebac
Reviewed-on: http://git-master/r/65290
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Rebase-Id: R557e282e415fd4bed871ea1ed8c056ae79731311
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Bug 841336
Reviewed-on: http://git-master/r/64931
(cherry picked from commit 1333406b624bd876cd31cada142d234f4e18b303)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Change-Id: Id62e0264962cd7511fc97e3c865f105ca10c65f0
Reviewed-on: http://git-master/r/65908
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Rebase-Id: R8561dc799000fb50a5fa0855133be2afcd2d992b
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