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2011-05-18arm: tegra: cardhu: set CPU EDP limitstegra-T30.ER5Varun Wadekar
Change-Id: I6282bbb63c34b8cc0d503cdd6eafe575fb78ef5f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/31342 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18ARM: Tegra: Support to update edp zonesVarun Wadekar
Tegra cpu-freq driver will now recognize edp zones and cap the max cpu freq for that zone. The temperature monitoring driver will be giving inputs to cpu-freq on the current temperature which would be interpreted by the cpu-freq driver appropriately. Change-Id: I918eb31771aa7e1e1a5f25438edded727de6eb8c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/31339 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-18arm: tegra: sensors: synchronize cam A and cam BPrayas Mohanty
For stereo camera support, both cam A and cam B should start at the same point of time to be in sync. bug 787214 bug 786928 Change-Id: I417db0f8ff8c76130b76d8edb4e66189d6b92447 Reviewed-on: http://git-master/r/30004 Tested-by: Prayas Mohanty <pmohanty@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-05-18ARM: tegra: power: Enable Tegra3 core DVFSAlex Frid
Enable Tegra3 core DVFS with default EDP limit set to 1.2V. Bug 812738 Bug 826200 Change-Id: If1e9f431729d0dbe6e8c89d9d8b9d5f9d2e8a2bf Reviewed-on: http://git-master/r/31254 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18ARM: tegra: baseband: Add PH450 modem init and reset functionsSteve Lin
Add PH450 modem init and reset functions for Tegra Enterprise. Bug 800301 Change-Id: I7068fa87118c2388badb664da3d1a83a3eb49dae Reviewed-on: http://git-master/r/30920 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18ARM: tegra: power: Use CPU LP mode for Tegra3 deep sleepAlex Frid
Change-Id: If23b48fb414332f5dd25307a098569a5474283c6 Reviewed-on: http://git-master/r/31471 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18arm: tegra: Set 48Khz default samplerateVinod G
bug 804696 Setting 48Khz as default samplerate as DAM SRC has issue with 44.1Khz Change-Id: I57119564c170a5d379df8917b82f6ea8992cc138 Reviewed-on: http://git-master/r/31269 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18ARM: tegra: clock: Set Tegra3 CPU maximum rate to 1.3GHzAlex Frid
Set Tegra3 CPU maximum rate to 1.3MHz. Effective only on boards with EDP table. Otherwise, the default EDP limit keeps rate below 1GHz. Change-Id: I8221cf037cc957b45cafc7f59c76d3cf25816228 Reviewed-on: http://git-master/r/31617 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2011-05-18ARM: tegra: power: Enable Tegra3 CPU EDP by defaultAlex Frid
Change-Id: I62ad3b3b7e0b4feba223c0dfe5792194aea6e4cd Reviewed-on: http://git-master/r/31616 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2011-05-18arm: tegra: power: Fix build break when CONFIG_PM disabledScott Williams
The code to select LP0/LP1 low-power mode via a sysfs node does not compile if CONFIG_PM is disabled. This fixes that error. Change-Id: If166759bd89f03335bca529cbe50a32420f802f6 Reviewed-on: http://git-master/r/31903 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2011-05-18ARM: tegra: Check if the cpu already booted or notvjagadish
Check the CPU is ever booted before entering into powerup status confirmation loop. BUG 824307 Change-Id: I474d0536b00e84967a240037d2ed984a889dd2e0 Reviewed-on: http://git-master/r/30679 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Venkata Jagadish <vjagadish@nvidia.com> Tested-by: Venkata Jagadish <vjagadish@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-18arm: tegra: cardhu: Adding board entry for tps6236xLaxman Dewangan
Adding platform data entry for the tps6236x device and registering this device if board info has sku with bit0 as 1. bug 821295 Change-Id: I18618ef75eca66a1f699c003c787dcb1f06e7659 Reviewed-on: http://git-master/r/31388 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2011-05-18arm: tegra: devices: Adding device details for tegra kbcAlok Chauhan
Adding device details for the tegra based kbc driver. Bug 827020 Change-Id: I47b150fc97f97ce91c1de569aec067ad2e5f0660 Reviewed-on: http://git-master/r/31725 Reviewed-by: Alok Chauhan <alokc@nvidia.com> Tested-by: Alok Chauhan <alokc@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-05-18ARM: Tegra: Enterprise: Fix Touchscreen gpios.Alex Odorovic
Fixes the issue with touchscreen feeling sluggish and not detecting all events. Bug 824702 Change-Id: I26f9a9d2192e445c79fe1830adac3dfc4e04ba4e Reviewed-on: http://git-master/r/31614 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Aleksandar Odorovic <aodorovic@nvidia.com>
2011-05-18ARM: tegra: touch: Add SKU for enterpriseTom Cherry
Change-Id: I60c16f4293e828d2960db734759184445d557555 Reviewed-on: http://git-master/r/31445 Tested-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Robert R Collins <rcollins@nvidia.com> Tested-by: Aleksandar Odorovic <aodorovic@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
2011-05-17ARM: config: cardhu: Enabling REGULATOR_TPS6236XLaxman Dewangan
Enabling the config variable CONFIG_REGULATOR_TPS6236X to support DC-DC converter device TPS6236x. bug 821295 Change-Id: Ibbab5f44d3d29517b4e5928a7a585887925afa22 Reviewed-on: http://git-master/r/31387 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-17ARM: tegra: cardhu: remove avdd_dsi_csi regulator codePritesh Raithatha
remove avdd_dsi_csi regulator code as it is already handled by tegra_camera.c Bug 826043 Change-Id: I0e97268c4381a27d9d2b499d7f332cc21314a045 Reviewed-on: http://git-master/r/31191 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-17arm: tegra: Add audio manager common interfaces.Vinod G
Audio manager common interfaces are defined to be called from SOC code. Audio manager will make the decision which all modules to be controlled based on use case connection. Correction added to the speaker amp and i2c gpio is provided for controlling the speaker amplification. Removed the speakersetting call. Change-Id: Id2c7f953fc78f66bee2e1d4773e03548de0ba5b4 Reviewed-on: http://git-master/r/30891 Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-17arm: config: Removing DUMMY REGULATOR from cardhu/ventana/enterpriseLaxman Dewangan
Removing the config variable REGULATOR_DUMMY from cardhu, ventana and enterprise as these boards have actual regulator. Change-Id: Ia39478b6adf887ca247cbf34bd8618b8ad463239 Reviewed-on: http://git-master/r/31136 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-17ARM: tegra: power: Add suspend index to cpufreq tableAlex Frid
Change-Id: I7bbe018f3786b9683cc9d4189fdcaadb9098f3f1 Reviewed-on: http://git-master/r/31456 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-17ARM: tegra: power: Update Tegra3 CPU DVFS tableAlex Frid
Change-Id: I3164bb2d86619b891a647b5e6550470c509eb403 Reviewed-on: http://git-master/r/31308 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-05-17ARM: tegra: power LP0/LP1 selection via sysfsKaran Jhavar
Select LP0/LP1 on runtime using sysfs node /sys/power/suspend/type. Valid selctions/commands are: 1. lp0 2. lp1 3. lp2 Change-Id: I335a8845dbfed7539ae4bf8aee3ba3b97ecb3db3 Reviewed-on: http://git-master/r/30081 Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2011-05-17ARM: tegra: clock: Enable clock while setting rate/parentAlex Frid
When clock configuration (source mux, divider value) changes, the new control register setting does not take effect if clock is disabled. Later, when the clock is enabled it would run for several cycles on the old configuration before switching to the new one. This h/w behavior creates two problems: - since dvfs takes into account only new (enabled) rate, the module can be over-clocked during initial phase of the clock switch - since parent clock refcount is updated when the mux register was written, the parent clock maybe disabled by the time of actual switch and h/w would not be able to complete switch at all To avoid described problems clock is now always enabled while setting the new rate/parent (and disabled afterwards to keep refcount intact). Change-Id: I9bda56a2a98c9f3678715da1e1b8fe78874fb71e Reviewed-on: http://git-master/r/31640 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-17ARM: 6355/1: hw-breakpoint: add mechanism for hooking into prefetch abortsWill Deacon
On ARM processors with hardware breakpoint and watchpoint support, triggering these events results in a debug exception. These manifest as prefetch and data aborts respectively. arch/arm/mm/fault.c already provides hook_fault_code for hooking into data aborts dependent on the DFSR. This patch adds a new function, hook_ifault_code for hooking into prefetch aborts in the same manner. This is picked from following git repository: git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-2.6.38.y.git Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: S. Karthikeyan <informkarthik@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> (cherry picked from commit 3a4b5dca53aecb16db9e007d782b2d1e757e941a) Change-Id: Ic278bad0e3bb95f504e46b216a8d14fd61fbc4a5 Reviewed-on: http://git-master/r/31574 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-17mach-types: Official tegra_enterprise machine numDan Willemsen
http://www.arm.linux.org.uk/developer/machines/list.php?id=3512 Change-Id: I432bd8512025c6f3ff312b8e120df37c68aa1153 Reviewed-on: http://git-master/r/31409 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
2011-05-13ARM: tegra: power: PM269: Add GPIO_REGPradeep Goudagunta
Adding GPIO_REG for power rails of PM269 board. Bug 823160 Change-Id: Idbb889420e033780900b1b1b700637017640414e Reviewed-on: http://git-master/r/30366 Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13ARM: tegra : power: Set power rails SATA & PCIE off by defaultKaran Jhavar
Setting SATA & PCIE power rails (ldo1 & ldo2) off by default since they are not enabled on Cardhu. Bug 793780, 790141 Change-Id: If905f156b99314271874536d61fe384715f2412a Reviewed-on: http://git-master/r/31292 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13ARM: tegra: enterprise: use UART4 as debug uartPradeep Goudagunta
Enable UART4 as debug uart. Bug 814271 Bug 822432 Change-Id: I73f01191d5f1e0fe979eb804028e0a7956eb93df Reviewed-on: http://git-master/r/30513 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13arm: tegra: nvmap: Forcing to convert CarveOut requests to IOVMHiro Sugawara
Adding a build time CONFIG option to enable forcing of conversion of non-IRAM CarveOut memory allocation requests to IOVM requests. Default is "y" to force the conversion. Each forced conversion is reported to console. Allocation alignments larger than page size for IOVM are enabled. Single page CarveOut allocations are converted to system memory. CarveOut memory reservation has been removed for aruba, cardhu, and enterprise. Change-Id: I3a598431d15b92ce853b3bec97be4b583d021264 Reviewed-on: http://git-master/r/29849 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13video: tegra: dsi: Adjusted the values of packet sequence registers.Kevin Huang
Changed the values of packet sequence registers for DSI burst video mode. Change-Id: I70188ed3c8fff094862a89377457751fd0d4382c Reviewed-on: http://git-master/r/31080 Reviewed-by: Kevin Huang <kevinh@nvidia.com> Tested-by: Kevin Huang <kevinh@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13ARM: defconfig: Cardhu: Enabling ARM erratasvenu byravarasu
Enabling arm erratas 743622, 751472 and 752520 for cardhu Change-Id: I0fb985a6bc78160683924875f14b2afbecba0604 Reviewed-on: http://git-master/r/31473 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-05-13media: tegra: avp: Use SMMU to load AVP kernelKaz Fukuoka
- Use nvrm_avp_e0000000.bin is for Tegra3 A01 - Use nvrm_avp_00001000.bin is for Tegra3 A02 and later bug 765965 Change-Id: I9bc28b122bd1b0cd2c1ece3bc681550de5912229 Reviewed-on: http://git-master/r/31202 Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com> Tested-by: Kaz Fukuoka <kfukuoka@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
2011-05-13ARM: tegra: power: Limit Tegra3 CPU nominal voltageAlex Frid
Limit Tegra3 CPU nominal voltage in case when maximum rate specified in the clock tree is below maximum rate in CPU dvfs table. Change-Id: Ie7b47a1f482f3c33da19e530b05663683bd807a1 Reviewed-on: http://git-master/r/31307 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-05-13ARM: tegra: clock: Support Tegra3 CPU clock fractional dividerAlex Frid
Added support for Tegra3 CPU super-clock fractional 7.1 divider: use it to adjust CPU rate, when super-clock parent is fixed rate PLL (for other parent PLLs with adjustable frequency set divider 1:1). Bug 821438 Change-Id: Ib8342330d103beb535af4d74ea51c46b9e25dc30 Reviewed-on: http://git-master/r/31219 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-05-13arch: arm: tegra: Bringup Enterprise touchscreen.Alex Odorovic
Bug 824702 Change-Id: I9eb48dee19b3d9e37843a83ee28e9ffb008ddd7e Reviewed-on: http://git-master/r/31077 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Aleksandar Odorovic <aodorovic@nvidia.com> Tested-by: Aleksandar Odorovic <aodorovic@nvidia.com>
2011-05-13ARM: tegra: power: Add out-of-range CPU dvfs entryAlex Frid
Change-Id: Ic50e6261e34caa3851ef68a6e2a6cbbd600a13d6 Reviewed-on: http://git-master/r/30929 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-05-13ARM: tegra: power: Set Tegra3 CPU/core rail nominal voltageAlex Frid
For different Tegra3 process corners/skus/revisions/boards set nominal voltages for CPU and core rails as well as adjust maximum clock rates as follows. - VDD_CORE rail nominal voltage: default value is indexed by speedo_id of the chip (speedo_id is determined by chip sku and revision). Minimum of the default and board specific electrical design voltage is rounded down against core dvfs voltage ladder. The result is set as nominal core voltage (edp voltage API is not implemented, yet). - VDD_CPU rail nominal voltage: default value is indexed by speedo_id of the chip. If too high, it is lowered to core nominal voltage so that core_on_cpu dependency is resolved at nominal core level. The result is compared with voltage required to reach CPU maximum rate as specified in the dvfs table for the particular process corner. Again, the minimal level is selected, and finally set as CPU nominal voltage. After nominal voltages are determined, maximum rate for each dvfs clock is adjusted accordingly, so that it does not exceed the rate specified in the respective DVFS table at nominal level. Change-Id: Ia6c1c5c853f98ab185f42bf1cfd7a1d7d54d10c3 Reviewed-on: http://git-master/r/30928 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-05-13ARM: tegra: enterprise: sdhci: Initial changesPradeep Goudagunta
Enterprise board uses SDMMC3 slot for External SD and SDMMC1 slot for WiFi. Bug 822432 Change-Id: Ifa13d69fa65f974c8457b9ffec231579b356a810 Reviewed-on: http://git-master/r/30514 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
2011-05-13arm: tegra: Exposing more i2s port for Baseband.Vinod G
Exposed the baseband i2s port for cardhu. Added separate audio init function. Change-Id: I9ff38f101c5540ad6e2365ed93a8c88373164ea3 Reviewed-on: http://git-master/r/30087 Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
2011-05-13nvhost: Add tracing to nvhost driver.Terje Bergstrom
Creates /d/tracing/events/nvhost. Logs channel opens, closes, writes and flushes. For writes, logs number, size and address of cmdbufs and number of relocs. Change-Id: I5bdadcb40c31e3f057eb8c4579b95e235d860e39 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/29770 Reviewed-by: Andrew Howe <ahowe@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
2011-05-11ARM: tegra: usb_phy: Fix USB compilation warningsRakesh Bodla
Removing unused variable. Change-Id: Idf5fd40c7a953505c08872023b3d55296237ec49 Reviewed-on: http://git-master/r/30690 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11arm: tegra: cardhu: Adding platform data for sh532u deviceLaxman Dewangan
Adding the board init and deinint function to power on/off rails for the sh532u autofocus driver. This function is passed as platform data to the driver. bug 802264 Change-Id: Ib7ef55898dce5f6ae458c922e6b5cbce64740cd0 Reviewed-on: http://git-master/r/30171 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11ARM: tegra: power: put IO_PAD to DPD during suspendJin Qian
Bug 814805, 767218 Change-Id: I818ebde2f7fd45152d1229ec257aa5f177d5253f Reviewed-on: http://git-master/r/30108 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11ARM: defconfig: Enable UVC USB camera supportYuvraj Pasi
Enable UVC driver to support the UVC usb camera. Disable usb suspend because if we enable it if fails to detect the usb camera sometimes. Bug 801763 Change-Id: I790739362a89ad04dbd356550a11a3920af12fde Reviewed-on: http://git-master/r/30025 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11arm: tegra: cardhu: Adding cam-AF power railsLaxman Dewangan
Adding the camera autofocus power rail infomration. Removing non-existant peripheral entry from i2c4 bus. Adding deselect mux option after each i2c transfer through mux i2c. bug 802264 Change-Id: Id87178666e4d8c4c5db3f8be708fc5fc85b3e2e4 Reviewed-on: http://git-master/r/29998 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11arm: tegra3: pinmux: Removing HDMI option from LCD_SCK/PWR0Laxman Dewangan
Removing the HDMI pinmux from pingroups LCD_SCK and LCD_PWR0 as per TRM document. Change-Id: I85e3a5fb3af1cecbe6eb83d47e811362cd4ee629 Reviewed-on: http://git-master/r/29970 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11ARM: errata: 727915: Background Clean & Invalidate by Way operation can ↵vdumpa
cause data corruption. PL310 implements the Clean & Invalidate by Way L2 cache maintenance operation (offset 0x7FC). This operation runs in background so that PL310 can handle normal accesses while it is in progress. Under very rare circumstances, due to this erratum, write data can be lost when PL310 treats a cacheable write transaction during a Clean & Invalidate by Way operation. This fix is to replace the background Clean & Invalby Way operation by a software loop on all sets/ways. This works for r2p0 and r3p0 as well. Change-Id: I45e841d8049a18f2dd36ce13e8ef15322f14c5d5 Reviewed-on: http://git-master/r/29690 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11ARM: defconfig: enabling PMU RTC on Cardhuvenu byravarasu
Enabled TPS6591x PMU RTC & disabled Tegra internal RTC Change-Id: I480ad99646b8eb57928a0b9c4d17fa0d6ed81d40 Reviewed-on: http://git-master/r/29636 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11ARM: tegra: restore voltage to nominal when rebootBo Yan
At the time of reboot, all rails need to be set to nominal to ensure the success of subsequent boot. bug 821969 bug 797082 Change-Id: Iee635c222619dfcb3e98f13e665ea2bd04e94245 Reviewed-on: http://git-master/r/30086 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11arm: tegra: ventana: deselect pca9546 i2c mux channel on exitNitin Kumbhar
On ventana, pca9546 is used as a mux for 0v2710/ov5650 camera sensors. With UJA0H14 version of ov5650 sensor, it is observed that pca9546 driver incorrectly caches last channel when VDDIO_CAM is toggled while enabling/disabling tegra camera. Deselect i2c mux channel on exit so that i2c mux is correctly configured with new mux channel. BUG 812134 (cherry picked from commit 2d62e589c0bd933db846d4b8f9fe4f2116bef8ad) Reviewed-on: http://git-master/r/29811 (cherry picked from commit c53b7eb26bee96fd7927e94848055af94baa831b) Change-Id: Ic41a952d05b610e569e37802cf05552af9d93e13 Reviewed-on: http://git-master/r/30975 Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-12-28 20:55:22 +0000