Age | Commit message (Collapse) | Author |
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Signed-off-by: Russell Robinson Jr <rrobinson@phytec.com>
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Signed-off-by: Russell Robinson Jr <rrobinson@phytec.com>
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Add platform support for Vybrid L2 switch driver.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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Add second FEC support for Vybrid.
Signed-off-by: Alison Wang <b18965@freescale.com>
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Add platform support for watchdog driver.
Signed-off-by: Wang Xiaojun <b41435@freescale.com>
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Add hardware flow control support,
Add transmit DMA support,
Add FIFO operation support,
Add MSB/LSB on data support,
Add 9-bits MARK/SPACE support.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
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Add platform support for Quad SPI driver.
Signed-off-by: Alison Wang <b18965@freescale.com>
Xiaochun Li <b41219@freescale.com>
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Add platform support for touch screen driver.
Signed-off-by: Alison Wang <b18965@freescale.com>
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Update platform support for dspi driver after debugging on board.
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Alison Wang <b18965@freescale.com>
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Four LEDS are connected to FTM0 ch0~3 on TWR-MVF600 board,
the PWM signal can use control these LEDS on/off or demo.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
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The FlexTimer work on PWM mode with EPWM and CPWM supported.
The API configures each FTM channels the same due to pwm subsystem
interface restriction.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
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Signed-off-by: Jingchang Lu <b35083@freescale.com>
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This patch enable the ADMA2 function for the SDHC module used
on Faraday board. Please note that the ADMA address should be 16
bytes aligned other than 4 byte in the spec.
This patch also increased the SDHC module frequency to 200MHz.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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Signed-off-by: Jingchang Lu <b35083@freescale.com>
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Enable the softecc in the config to make the NFC use softecc.
also include the defconfig update for:
ENGR220009:The LCD panel goes blank after a long time
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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This patch increase the delay time for the pll clock to lock. otherwise
the kernel will panic for the locking failure.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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The PKE and PUE should be declared for the GPIO pull up, otherwise the pin
will not be pulled up for the SDHC card detect input.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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Add default kernel config for Faraday.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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OTG1 acts as gadget and OTG2 acts as host on TWR-MVF600 board.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
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Add platform support for dspi driver.
Signed-off-by: Alison Wang <b18965@freescale.com>
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Add platform support for SAI driver.
Signed-off-by: Alison Wang <b18965@freescale.com>
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Add platform support for dcu driver.
Signed-off-by: Alison Wang <b18965@freescale.com>
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Add platform support for NFC driver.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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Add platform support for RTC driver.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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Add platform support for I2C controller.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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Add platform support for edma driver.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Xiaochun Li <b41219@freescale.com>
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Add platform support for esdhc driver.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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Add platform support for FEC driver.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
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Add platform support for UART driver.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <b35083@freescale.com>
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Add gpio API for MVF platform.
The MVF GPIO framwork is different with i.mx.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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Add IOMUX definiation and initialization.
Add the iomux initialization support for Faraday.
Define the io pad settings for some function modules. Those
pad ctrl settings may need to adjust during the feature tuning
process.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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Add MSL support for MVF platform.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Jingchang Lu <b35083@freescale.com>
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This patch adds processor info for ARM Ltd. Cortex A5,
which has SCU initialisation procedure identical to A9.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 15eb169bfec291faf25b158cfa9842b72f7803ad)
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The PMUv2 specification reserves a number of event encodings
for common events.
This patch adds these events to the common event enumeration
in preparation for PMUv2 cores, such as Cortex-A15.
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 6d4eaf991c654af54a19c0fa48e0ad62cefbc37c)
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As most of the proc info content is common across all v7
processors, this patch converts existing A9 and generic v7
descriptions into a macro (allowing extra flags in future).
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit dc939cd835d0e2d3ff4197d6e2c017d269616d20)
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This patch adds support for the Cortex-A5 PMU to the ARMv7 perf-event
backend.
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 0c205cbe20654616e2f8389c0c1ff707d9dccb63)
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Previous PLL1 freq change is done by switching CPU clock
to 400M pfd or 24M OSC, then modifying
PLL1 div directly, and switch back CPU clock immediately,
it will result in CPU clock stop during PLL1 hardware lock
period, thus, DRAM FIFO may blocked by the data CPU
requested before PLL1 clock changed, and it will block other devices
accessing DRAM, such as IPU, VPU etc. It will cause
underrun or hang issue. We should wait PLL1 lock, then switch
back.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The host driver needs to differentiate wakeup event.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Enable local timer by default. If wait mode is on,
local timer will be shutdown automatically on boot.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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After a cpufreq transition, update the clockevent's frequency
by fetching the new clock rate from the clock framework and
reprogram the next clock event.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
Signed-off-by: Colin Cross <ccross@android.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add a smp_twd system clock which is simple clock
from parent of cpu_clk, and it's rate is half
of the cpu_clk.
This is used for reprograming the twd clock event
after cpu freq is changed.
Also disable local timer setup when wait mode enabled.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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remove SION bit for SD3_CMD pad control, it will enlarge clock tuning
window on MX6DL.
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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change clock debugfs sys attr 'enable_count' to 'usecount'
to align with some power debug tool used
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Added the new 1.2GHz working point.
Currently 'arm_freq=1200" should be added to commandline
for the core to run at 1.2GHz. Also ensure that the appropriate
HW board mods have been done to set VDDARM_IN at 1.425V.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix a typo when adding 600M WP, the voltage value is wrong,
it will lead a warnning when change to this WP:
COULD NOT SET GP VOLTAGE!!!!
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Remove audio platform data rst_gpio which is not longer required now.
Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
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*Files affected: board-mx6q_sabreauto.c
*Added IOMUX settings for parallel nor
*Utilized physmap driver in order to probe the chip
*Implemented conditional compilation enabling either spi or parallel
nor.
Signed-off-by: Francisco Munoz <b37752@freescale.com>
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Change mclk sensor name to clko_clk
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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