Age | Commit message (Collapse) | Author |
|
Enabling cdev1 clk or DAP Mclk from board file instead of
codec soc file because Mclk needs to be enabled before
codec initialization. Also exposing set_parent() for cdev
clocks so that it is possible to enable them from board
file.
Bug 827709
Bug 839210
Bug 821178
Change-Id: I6e0e15be9f9a2da98ce2ba89e3390bef1e2b93a7
Reviewed-on: http://git-master/r/37631
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
|
|
Removed the semicolon after 'if'.
Change-Id: I91df7b367633e269116110b3469c1efcb2589a95
Reviewed-on: http://git-master/r/37459
Tested-by: Jubeom Kim <jubeomk@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
|
|
MMC_BLOCK_DEFERRED_RESUME causes race conditions in the SD/MMC driver,
i.e. mmc_sd_detect() will be called from different threads causing
inconsistent state. Disabling feature for Tegra.
Bug 833034
Change-Id: I516272a5a0af44ba27122cc0c6476512cf5b617d
Reviewed-on: http://git-master/r/36254
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
|
|
Bug 820602
Change-Id: I6a5f116cc3c32f58a7404de24a073ddaf2c79227
Reviewed-on: http://git-master/r/35954
Tested-by: Cho-Che Cheng <jacheng@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
There was no code to clear interrupt registers for AVP. First run
of AVP was OK because those registers start from reset value.
But because those registers were not cleared, when the second
time AVP was started, some interrupts were enabled too early.
That caused interrupts coming before handlers were ready.
This change also removes the workaroud for the bug.
bug 827353
bug 826234
Change-Id: I21876a4d2a8d729def9f43a0f8879e1de3e84dde
Reviewed-on: http://git-master/r/33083
Reviewed-on: http://git-master/r/35355
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Bug 814896, 820602
Change-Id: Ief590e49f995dd1da6502707ac329057a12f4f17
Reviewed-on: http://git-master/r/35948
Tested-by: Cho-Che Cheng <jacheng@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
- handle scenarios when the number of fuses burnt
is a odd number
- wait for the fuse bock to be idle before issuing
any command
- burning of master_enb fuse is not required to be
done according to the guidelines
Bug 823552
Change-Id: I04477dcfae610aed3e2072adfc48ebd7212449ad
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/35883
Reviewed-by: Andy Carman <acarman@nvidia.com>
Tested-by: Andy Carman <acarman@nvidia.com>
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
use FB_BLANK_POWERDOWN on hdmi device in earlysuspend to cause
tegra_dc_disable.
Fixes bug 835171
Change-Id: I112d05f271b9d12319186ff1b9bd2d0e0667a75e
Reviewed-on: http://git-master/r/35412
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Added regulator vmic to use in soc-audio
Reviewed-on: http://git-master/r/33110
(cherry picked from commit 1b5f6d90219d6e3beeaeb2ec286949bc838d9bc4)
Change-Id: Iba33f5bf2bc5243ff13995005d1c182f6d120d55
Reviewed-on: http://git-master/r/35375
Tested-by: Viraj Karandikar <vkarandikar@nvidia.com>
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
|
|
disabling ldo4 kills power to the board completely.
there is no way to power on the board again, other
than reinserting the power plug.
Change-Id: I1e03389cf26ad8de7a5d5fb518f85fa6c9427752
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/35620
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
This option adds support for ASIX AX88xxx Based USB 2.0
Ethernet Adapters and it works with TrendNet TU2-ET100 devices.
Bug 834417
Change-Id: I46d3990e72c66b6abc2821b7e70d039718bbf487
Reviewed-on: http://git-master/r/35699
Reviewed-by: Vandana Salve <vsalve@nvidia.com>
Tested-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Extend the wait interface to relay the actual resultant waited
point back.
Reviewed-on: http://git-master/r/23033
(cherry picked from commit bc22c56ecb54ec093262cee4b1105c2503e5497e)
Change-Id: I65224359f85d3f357e48eeacdf76c9bd97056a54
Reviewed-on: http://git-master/r/35919
Reviewed-by: Brian Anderson <branderson@nvidia.com>
Tested-by: Brian Anderson <branderson@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
|
|
Passing card detect gpio polarity through platform data.
This is used in sd cards insertion/removal detection.
Bug 831409
Change-Id: I29c99696daf094d4f04789121ddfb681dccca12a
Reviewed-on: http://git-master/r/33123
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com>
Tested-by: Joseph Lehrer <jlehrer@nvidia.com>
|
|
Hotplug does not work if the regulator is disabled, so keep it enabled
until the device wants to enter lowpower mode.
Change-Id: I5a53a0fb0a7f26ba9f2674bbc65f4650948f6143
Reviewed-on: http://git-master/r/33117
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
Change-Id: I6ec62abdaf3a8ec2e59e2a533b36b280d69538e1
Signed-off-by: Ari Hirvonen <ahirvonen@nvidia.com>
Reviewed-on: http://git-master/r/33037
Reviewed-by: Michael I Gold <gold@nvidia.com>
Tested-by: Michael I Gold <gold@nvidia.com>
|
|
Enabling AHB prefetch on USB1, USB2, USB3 controllers,
to improve the USB transfer throughput.
Bug 820602
Change-Id: I4e9e9fa37624cc11f83effd268cdbf31c01f1df7
Reviewed-on: http://git-master/r/30475
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
|
|
Change-Id: I2dcdfadb44a981cccf583a156be0be093ca5feec
Reviewed-on: http://git-master/r/34229
Reviewed-by: Maria Gutowski <mgutowski@nvidia.com>
Tested-by: Maria Gutowski <mgutowski@nvidia.com>
|
|
this is done so that it's easy to get the emc stats without having to
enable this explicitly when one wants to get the emc stats.
Change-Id: Id6039e8cb4510740182981245453128f406ee00d
Reviewed-on: http://git-master/r/32171
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Assignment moved inside if statement, where it belongs.
bug 828756
Change-Id: I2ee63bed168feade897ba15b364de1ee714f1381
Reviewed-on: http://git-master/r/31955
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
|
|
tegra_dc_hdmi_equal doesn't check pixclock. some devices doesn't
support 14.85Mhz pixclock so 1080p@60 cannot be used. However,
1080p@30 is supported. Therefore, adding a max pixclock prevents
1080p@60 mode is falsely used for those devices
Bug: 815409
Change-Id: Ia2d8dcf360afa51e160d0e997986fe1714254a6b
Reviewed-on: http://git-master/r/31663
Reviewed-by: Donghan Ryu <dryu@nvidia.com>
Tested-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Add support for usb hotplug, this change will add the following:
vbus is left enabled.
Bug 796158
Change-Id: I3c3cfa0bf8858b3be2351fe753ceb2a0229ed15d
Reviewed-on: http://git-master/r/30686
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
|
|
added code to support digital mic on wm8903 for ventana. By default
analog mic is enabled. To enable digital mic write 1 and to disable
write 0 to
/sys/devices/platform/soc-audio/enable_digital_mic
Change-Id: I36e239d10404a9bc8446e275e5c59e9829409608
Reviewed-on: http://git-master/r/29615
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
|
|
sclk max rate for AP25 is 300MHz and pclk is set as 1:2 to sclk.
pclk max rate changed to 150MHz for AP25.
Bug 821534
Change-Id: I6c6b30f0c9b2dd568e6171e9b6d88c8eef212ab7
Reviewed-on: http://git-master/r/31311
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
|
|
The kernel now receives wait tracking data (similar to gathers and
relocs) and compares the current syncpt with the threshold value.
If it's old, it gets a kernel mapping and rewrites the method data
to use a kernel reserved syncpt that is always 0 (so trivially pops
when seen by the HW).
Bug 519650
Bug 785525
Bug 803452
Note: reset the author in this commit to fix a email addr problem
and since from the latest/last cherry pick there was a reworking
of the code to be compatible with different user space versions
it also seemed reasonable.
(cherry picked from commit 4069d8e67665624ad3dceb628e572980dd57acd0)
(cherry picked from commit 6e4336408588e348804a62e53386acc9abc06823)
(cherry picked from commit 87a9efe751716ca741caac72b9061fdfdcec540a)
Change-Id: I9c6076da2384f373d5f402bee4406b09b4ebc4ff
Reviewed-on: http://git-master/r/23159
Reviewed-on: http://git-master/r/30281
Tested-by: Chris Johnson <cwj@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>
|
|
Merge updates from tegra_defconfig
Change-Id: I45a488f27c516a0f892eb394771302c68cd2aa6c
Reviewed-on: http://git-master/r/31257
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Andrei Denissov <adenissov@nvidia.com>
Reviewed-by: Jonathan B White (Engrg-Mobile) <jwhite@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
|
|
Set the platform data for the USB1 host mode to NULL during the unregister.
After freeing up the platform data pointer.
Bug 820333
Change-Id: I6fb3edf58d854c0d8f648572f40cebe6811e2069
Reviewed-on: http://git-master/r/30696
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Change-Id: Ic3eb5d136be746b55bea4efe302e0f417dfc1eb6
Reviewed-on: http://git-master/r/30512
Tested-by: Manjula Gupta <magupta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
|
|
Bug 803932
Change-Id: Ia9cf3f20c6921fc18b02527c9c0108fd4f08e79b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/30195
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
shared clock rate is dependent on its parent max rate. Parent's max rate
get updated in sku limit init depending on the sku value. Hence initialize
shared clocks after sku limits are applied.
Bug 821534
Change-Id: Ic11631cd54af638c8afa75aceeb4bcd999c8135f
Reviewed-on: http://git-master/r/30504
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
|
|
dynamic changing of pclk divider to follow APB clock minimum
frequency requirements with respect to sclk frequency.
Bug 819796
Reviewed-on: http://git-master/r/29643
(cherry picked from commit c5ed952608ff2e3ffdcba99295f8892dac1506c0)
Change-Id: Iec403b137fa001ff401fd14990040889ec679eca
Reviewed-on: http://git-master/r/30315
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
sclk continues to be clocked at 120MHz even when there is no activity.
Add dfs so that different modules can set sclk rate as required and it will
be clocked to minimum when there is no activity.
Minimum limit changed to 40MHz for sclk.
Bug 819796
Reviewed-on: http://git-master/r/28764
(cherry picked from commit ee17dca953c7eadc01a221a245a7e95d0fff33ea)
Change-Id: I78d4a6b699bb827de4d5cfa5ac621961d09d47de
Reviewed-on: http://git-master/r/30313
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Revise some default settings for utimp phy
Bug 815848
Change-Id: I7eac6981e52bdf6b33e80d34aebb0dc403b326bf
Reviewed-on: http://git-master/r/30257
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
some testing revealed certain loopholes in the
code. also the way the shell sends data down to
the sysfs handlers changed which warranted the
change in the handlers.
Change-Id: I131ab43691321a864ad5afd4f9852a7ba8842130
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/30134
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
This is to make sure this function will not cause any lock-up
during actual reboot
Should help bug 770426
Change-Id: Id5cfaee07d9438741b721b67c7cd342858e7b5cb
Reviewed-on: http://git-master/r/28345
Reviewed-on: http://git-master/r/30176
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Disabling IRQ and FIQ before we stop other processor cores and start reboot
process will make sure the restart procedure is not preempted. This is to
prevent the potential lockup caused by the loss of synchronisation among
different processor cores due to IPI_STOP.
Should help bug 770426
Reviewed-on: http://git-master/r/27780
(cherry picked from commit 3d63b7709f3614783ebbf97568132458e5198c29)
Change-Id: I513a1f7394478b16f6c0204af7b31b18244ac819
Reviewed-on: http://git-master/r/30172
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
LDO_SHDN_L signals control AVDD_2P8V and VDD_AF_2P8V supplies to
camera sensor modules. Power on these supplies only when camera
is in use.
BUG 782390
Change-Id: Ifefbb0b4da0b9213c4a2f76b51bcd3f2bbeb745d
Reviewed-on: http://git-master/r/30015
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Erik M Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
On ventana, pca9546 is used as a mux for 0v2710/ov5650 camera
sensors. With UJA0H14 version of ov5650 sensor, it is observed
that pca9546 driver incorrectly caches last channel when VDDIO_CAM
is toggled while enabling/disabling tegra camera. Deselect i2c
mux channel on exit so that i2c mux is correctly configured with
new mux channel.
BUG 812134
(cherry picked from commit 2d62e589c0bd933db846d4b8f9fe4f2116bef8ad)
Change-Id: Id249bbeb33c370b8fc5360af33bdefecfd62a48a
Reviewed-on: http://git-master/r/29811
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Erik M Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Change-Id: I26f58048e4bb2988a7121bf4a7738607ced88a12
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/29674
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
* add bsea engine support for encryption and decryption
* add arbitration semaphore id for bsea
Bug 803932
Change-Id: I978b06a12265acecae99dbf13607e00ae74e87f7
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/29672
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
program pwren signal of max8907c regulator to power down/up core rail on
deep sleep enter/exit deep sleep mode.
core_timer and core_off_timer changed as per K32.
separate_req set to false as whistler pmu has combined power requests.
Bug 817378
Change-Id: Ia95a61360079f919a039572cf8fd4597db9efd50
Reviewed-on: http://git-master/r/28435
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Conflicts:
arch/arm/mm/proc-v7.S
drivers/video/tegra/dc/dc.c
Change-Id: I40be0d615f14f1c01305388a706d257f624ba968
|
|
|
|
Rabin Vincent reports:
| On SMP, this BUG() in save_stack_trace_tsk() can be easily triggered
| from user space by reading /proc/$PID/stack, where $PID is any pid but
| the current process:
|
| if (tsk != current) {
| #ifdef CONFIG_SMP
| /*
| * What guarantees do we have here that 'tsk'
| * is not running on another CPU?
| */
| BUG();
| #else
Fix this by replacing the BUG() with an entry to terminate the stack
trace, returning an empty trace - I'd rather not expose the dwarf
unwinder to a volatile stack of a running thread.
Change-Id: Ide38bb5eeff09c1d1189bc1a30667a2cc6b96ba2
Reported-by: Rabin Vincent <rabin@rab.in>
Tested-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Reviewed-on: http://git-master/r/28325
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
|
|
Change-Id: I5cdfdfef8dfc9ff4796e8a9b53d9af8f41e49e65
Reviewed-on: http://git-master/r/24360
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
|
|
- configured the pinmuxes needed by the baseband.
- added board specific baseband related code.
- added caif specific platform data needed by protocol layer.
bug 785523
Change-Id: I2d1936419ccd9190d6539836cb8bca563ea07c6e
Reviewed-on: http://git-master/r/23432
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
|
|
Fix SSL3250A camera flash I2C errors.
Bug 778859
Change-Id: I086eb863cce343a107f5f382d2b96eecf70d6902
Reviewed-on: http://git-master/r/28202
Reviewed-by: Erik M Lilliebjerg <elilliebjerg@nvidia.com>
Tested-by: Erik M Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-by: Prayas Mohanty <pmohanty@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Bug 803932
Change-Id: Idfafba37e71e80bce1b70a7324daf5e8df2a9e0d
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/28174
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Bug 803932
Change-Id: I52703d6281bf613d7ccf67c38daf6412ac790c74
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/28173
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Bug 803932
Change-Id: I61cf41423d08d2f2c19f314269be9e8ee6255b9b
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/28172
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Add registration and initialization of soc380 camera
Bug: 783488
Change-Id: I9ad9d25cfa51a45b2fe889cdac5b90650eafdd03
Reviewed-on: http://git-master/r/24973
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
|