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To achieve lower power number in low power idle, on the boards
which has higher vddhigh_in than vddsnvs_in, need to dis-connect
vddhigh_in and vddsnvs_in internally to make vddhigh_in's power
low enough to meet the design target.
Signed-off-by: Anson Huang <b20788@freescale.com>
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This patch add the 9x9-evk-csi.dts for the camera module
since the csi-camera has the pin conflict with sim module,
this patch is to enable the camera module while disable sim.
Signed-off-by: Jason Liu <r64343@freescale.com>
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Update max voltage of SW1A to 3.3V on PF3000, see below datasheet:
http://cache.freescale.com/files/analog/doc/data_sheet/PF3000.pdf?fsrch=1&sr=1&pageNum=1
Signed-off-by: Robin Gong <b38343@freescale.com>
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Add LDO enable dtb for i.MX66UL-9x9-EVK board for those customers
who want to use ldo enable mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
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i.MX6UL-9x9-EVK board has PFUZE3000, enable LDO bypass support.
Signed-off-by: Anson Huang <b20788@freescale.com>
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This patch adds suspend/resume with Mega/Fast mix off
support for i.MX6UL-9x9-LPDDR2-EVK board, LPDDR2 has
different MMDC restore flow compared to DDR3.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add i.MX6UL-9x9-LPDDR2-EVK board support.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The SD CLK signal measured by scope shows the signal rise/fall time
does not meet the spec requirement, need increase the pad driver
strength to meet the spec.
The pad setting value is given by the HW team which has been verified
from scope.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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ARM/MP: 814220—B-Cache maintenance by set/way operations can execute out of order.
Description:
The v7 ARM states that all cache and branch predictor maintenance operations
that do not specify an address execute, relative to each other, in program
order. However, because of this erratum, an L2 set/way cache maintenance
operation can overtake an L1 set/way cache maintenance operation, this would
cause the data corruption.
This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.
This patch is the SW workaround by adding a DSB before changing cache levels as
the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation.
Signed-off-by: Jason Liu <r64343@freescale.com>
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Change the property 'fsl,pin' to 'fsl,pins', otherwise the pins
setting can't be recognized.
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
(cherry picked from commit ee173ffef55dce980583f35b56509c98a788f886)
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Add dts for mx6ul-14x14-lpddr2-arm2 board.
Basic function tested: SD1/EMMC2/ENET/UART1 is ok.
This patch takes mx6ul-14x14-ddr3-arm2.dts as a reference.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit a8eaa148f6577059b4034fb0fb2d399effb2cace)
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On one board EB15140079 the Broadcom switch phy ID is 0x600d8599.
Add the phy fixup for the board support.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: 5ab17ce68acab43697c8fb4a38d46c3e423d4b91)
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In i.MX6UL clk driver code, some comments are incorrect
and some are NOT needed now, improve them.
Signed-off-by: Anson Huang <b20788@freescale.com>
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- Add CONFIG_USB_OTG_WHITELIST and CONFIG_USB_HCD_TEST_MODE
- Change CONFIG_USB_EHSET_TEST_FIXTURE from 'm' to 'y'
Signed-off-by: Peter Chen <peter.chen@freescale.com>
(cherry picked from commit 40f0d728339fb460a108bc8b133207dd5a17dda8)
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In tsc2046 touch driver, the values such as ti,x-min is defined as a u16
value. the driver use API of_property_read_u16() read the value. For these
u16 value, the dts entry should be like:
property = /bits/ 16 <0x5000>;
This describe the property as a u16 value.
if the dts entry write like following:
property = <0x5000>;
of subsystem will read this property as a u32 value in default. Due to the
DTB file is big-endian, and our memory system is little endian, this will
make the driver can't read the correct value.
This patch correct the format of u16 values, and set the default value defined
in tsc2046 touch driver.
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
(cherry picked from commit d1e680a0d20ac88e9bbcc7c4a7008999d79ca322)
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Disable all otg features for otg1 port of imx7d-sdb board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit 3c59511b7eac99da8c9bd373b82ddcbf61d1ef8a)
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Disable all otg features for otg1 port of imx7d-12x12-lpddr3-arm2 board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit 8d19fb5979522032cf4d96909d609aceac0dde85)
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Disable all otg features for otg1 port of imx7d-12x12-ddr3-arm2 board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit d74b978c52f0af09195e1a592643335c74112890)
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Disable all otg features for otg1 port of imx6sx-sdb board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit e8d32c2cc5daab7e22f6190a02c88981aa14df7e)
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Disable all otg features for otg1 port of imx6sx-sabreauto board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit 4c3191e538309bef9ac6f9effb9d698d52699a1a)
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Disable all otg features for otg1 port of imx6sx-19x19-arm2 board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit e83384609ba0e8daf8d9f87abb4ef3d81dd0ca79)
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Disable all otg features for otg1 port of imx6sx-17x17-arm2 board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit 46d2433c7e8e8b89352c823a6ccf267d3ac7882b)
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Disable all otg features for otg1 port of imx6sl-evk board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit 855c996b52317760e114e7884810a0b438b6e3ee)
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Disable all otg features for otg1 port of imx6qdl-sabresd board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit 71ed636ea10843cc2aac46711adf2350a34fa7b0)
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Disable all otg features for otg1 port of imx6qdl-sabreauto board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit b4082a9456f735b664fd125e2e6964963ac9c8d0)
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Disable all otg features for otg1 port of imx6q-sabrelite board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit 790186e23d544146938c069935e4f10ccca1abbe)
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Disable all otg features for otg1 port of imx6q-arm2 board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit 70c4fe93ac7064f5128ae2275b766fb00c4cd6ef)
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Disable all otg features for otg1 port of imx6ul-14x14-ddr3-arm2 board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit aad5b76e0e2743fb9564c833c1f55d4f6ea65efe)
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Same as i.MX6SX, need to disconnect vddhigh and vddsnvs
in DSM on i.MX6UL, they have same design.
Signed-off-by: Anson Huang <b20788@freescale.com>
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per design team's recommendation, in DSM mode,
need to disconnect vddhigh and vddsnvs, add it for i.MX6SX.
i.MX6SX has different bit definition than i.MX6SL about this
bit in PMU_MISC0 register.
Signed-off-by: Anson Huang <b20788@freescale.com>
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on imx6ul evk board
For the i.MX6UL EVK board, according to the latest schematic, use a GPIO pin along with
the 'PMIC_STBY_REQ' pin to control the DC-DC voltage output. the possible voltage output
as below:
PMIC_STBY_REQ = 0, GPIO_DVFS = 0, output is 1.4V (1.375V + 25mV) <Default>
PMIC_STBY_REQ = 0, GPIO_DVFS = 1, output is 1.3V (1.275V + 25mV)
PMIC_STBY_REQ = 1, GPIO_DVFS = 0, output is 0.925V (0.9V + 25mV)
In normal run mode, the voltage output should be changed using the 'GPIO_DVFS' pin,
so add gpio regulator to control it.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit 4517cf404b4e0cfb805a9d0c412b2f2839400d9b)
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Updating the setpoint data on i.MX6UL According to the latest
datasheet(Rev. B, 04/2015). Additionally, we add a 25mV margin
to cover the board tolerence and IR drop.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit 20b60a54ca413ff4183b895c247794f3f7626e69)
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Due to the clk tree info for AXI/AHB updating on i.MX6UL, the
busfreq enter/exit on i.MX6UL also need to be updated to align
to these changes. The AXI/AHB should be source from pll2_bus, and
the AHB clock divider value need to be set to 4 to make sure when
exiting from low bus mode, the AHB clock is also the original rate.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit e19096fae5c9c692d8bb560db10771dee34b3c10)
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According to the latest reference manual, the default AXI clock rate
should be 264MHz. Soucre AXI/AHB from pll2_bus to get the required
clock rate.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit 8221b17e0adb10f780f0fcf7d683148caa129eca)
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For low power idle with ARM power gated, per hardware requirement,
there must be no interrupt coming during the power down
process of ARM core, so RBC counter is enabled to hold interrupts.
However, the previous setting of RBC counter is 1, which is ~30us,
but the hardware design recommend a ~90us is required during ARM
core power down, so we update the RBC counter value to 4(~120us) here.
Previous delay loop to make sure RBC is actually enabled, 3us is
needed, but the loop value assume ARM is running @1GHz, but actually
ARM is running @24MHz now, so we need to update the loop value
according to ARM speed.
The ARM power up timing is based on IPG / 2048, IPG is 1.5MHz during
low power idle, so the total latency of cpuidle exit should be
updated accordingly.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 6d6dc82a4888f936cd2fde968e4f4854c2181eb8)
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On different platforms, the CPU power down/up timing may be
different because of different requirements or different
implementations in hardware, so we need to support dynamic
setting of these timing, board level dtb file will provide
these settings, and GPC driver need to read them and set them
to the hardware.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 05ee383bb4cfdab29b8c1e97da63422b25115bdf)
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On i.MX6UL, the cpu power down/up timing clock source is changed:
PGC_CPU_PDNSCR: ISO2SW ipg
PGC_CPU_PDNSCR: ISO ipg
PGC_CPU_PUPSCR: ISO2SW ipg / 2048
PGC_CPU_PUPSCR: SW ipg / 2048
To speed up the cpu power down/up process, need to adjust these
counters' value to the smallest setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 0cf4368db700043d9a8a97fbb5d4b48e56640324)
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Adding 'is_prepared' callback function for pllv3 type clk to make sure when
the system is bootup, the unused clk is in a known state to match the prepare
count info.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit df0d57db7fe32a3be778fa7c4f81ee4c47203237)
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If in low power idle, we use the RC-OSC to reduce the power consumption,
the RC-OSC freq need to be adjusted, otherwise, the RC-OSC freq is not
very accurate. It may lead to system instability issue.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit d46bf0b55942e20813382be58862aa67bfb8751b)
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The VSELECT for 1.8V does not work on PMIC board, so should not use
it for SD1.
Signed-off-by: Ye.Li <Ye.Li@freescale.com>
(cherry picked from commit 7c8fbfea57590904df4f9ed8d5d3bbae4d27a597)
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Add CAAM jr irqs to the gpc mf-mix-wakeup-irq mask to allow the Job Rings to
register as wakeup devices. Fixed both 6UL and 7D configurations to cover all
available Job Rings.
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
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This bit is used to keep the ARM Platform memory clocks enabled if
an interrupt is pending when entering low power mode. This bit should
always bet set when the CCM_CLPCR_LPM bits are set to 01(WAIT Mode) or
10 (STOP mode) without power gating.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Add CAAM snvs/secvio device tree nodes to enable the driver..
Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
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iMX7D DDR3 ARM2 board LCDIF pin confilict with CSI,
so disable LCDIF in csi dtb.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit 7099bf4b77165b547512c34b27709cdaf4d07fde)
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Keep the mu rpmsg int always enable.
- rpmsg transmissions are async, and drived by mu interactions
between the amp cores.
- the schedule delay is not real time mechanism, the mu
interactions maybe blocked by the previous rpmsg int disable
when there are very quick intercations between the amp cores.
Solution:
Keep mu rpmsg int always enable, since it is just to notify
rpmsg master that there is buffer to read, and can be re-entry
multi-times.
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
(cherry picked from commit 8487604b25aec5ef50ed865c2ccf2766eb658e78)
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Populate i.mx6ul device tree with third Job Ring configuration.
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
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When SMP is deselected, ARM_ARCH_TIMER is still enabled while
broadcast time is disabled, so when system enters WAIT mode,
ARM platform's clock will be disabled, then system tick timer
will stop and cause system stay at WAIT mode and timer event
will NOT come as expected.
To fix this issue, we do runtime check in our timer driver,
if SMP is NOT enabled, ARM_ARCH_TIMER will be disabled and
using GPT timer always.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Update the TEMPMON node properties on i.MX6UL.
Signed-off-by: Bai Ping <b51503@freescale.com>
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By doing this, we can allocate memory from iram when using i.MX7D SoC.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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By doing this, we can allow SDMA driver to allocate its memory from
iram when using i.MX6UL SoC.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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