Age | Commit message (Collapse) | Author |
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Add a hackish way of enabling USBH_PEN as required for USB host port on
Iris.
Please note that for now this is not integrated with USB class stuff.
Just direct straight GPIO enabling.
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Setup at least a 128 MB big mapping analogous to the following:
5761904d59d84fadadc65de306cb1cba17f49e2a
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Enable RTS/CTS on UART_A aka UART0 and UART_B aka UART2.
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Integrate backlight using both BL_ON GPIO and PWM<A>.
Note: Just disabled PWM LEDs for now (e.g. first need to figure out how
the mapping of different FTMs to their channels actually works).
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Re-work pin muxing:
- FTM aka PWM without open drain enable
- DSPI1
- USBH_PEN, USBC_DET and USB_OC
- EXT_AUDIO_MCLK
- clean-up touchscreen pins
- BL_ON
- UART0 RTS/CTS and UART2
NAND pins are still missing (e.g. rely on U-Boot already having
done their configuration.
While at it clean-up includes as well.
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Disable magic SysRq key configuration as this is not only a potential
security thread but can cause serious trouble if for some reason UART
pins are left floating and therefore cause unexpected break conditions.
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Decrease DMA zone size configuration analogous to Freescale's tower.
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Enable TMPFS POSIX ACL configuration to avoid systemd errors of the
following kind:
[ 27.619666] systemd-logind[269]: Failed to apply ACLs: Operation not
supported
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Re-enable resp. do not explicitly disable L2 cache configuration after
it now properly checks whether or not L2 cache is actually present at
all:
57a25827428efb7e8cc2eb6e59c529b5093a98e5
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to occur when using USB1.
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L2 cache is not present.
Author: Roshni Shah <roshni.shah@timesys.com>
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Enable the Colibri VF50 touchscreen driver by default when using
default configuration for Colibri VF50.
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The touchscreen support backed by hardware on the Colibri VF50
module and the Vybrid ADC is now moved to a own module for better
maintainability. The mvf-adc driver exports some of its method
now. A good good locking mechanism is still missing.
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In order to be more energy efficient sample the ADC channels only
if touch is detected. Do the pinmux in the platform specific code,
extended the platform data with those helper functions.
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The Vybrid VF50 support 4-wire touchscreens using FETs and
ADC inputs. This drivers extends the ADC driver to deliver
initial support for this interface.
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In order to use GPIOs in floating mode, the GPIO driver should not
alter the muxing settings made by pinmux. This patch reads the
current muxing settings and alters only the direction.
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Add clock information and platform data for ADC1. Those data are
used by the driver to create the second ADC instance.
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Touchscreen will be supported through ADC and some GPIOs. This
change adds proper pinmux, no driver support yet.
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This reverts commit f8852e8d0595f6c3f9d2073d45d6e3cbc52816c6.
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Get rid of the unused NAND controller driver platform data.
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Disable NAND controller software ECC in order to use hardware ECC.
Enable ADC driver as well as debugfs file system.
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Increase display pin drive strength by terminating with 75 instead of
150 ohm.
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Set DCU clock to 150.7 MHz which allows further dividing to VESA
compliant pixel clocks.
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Fix rounding in the DCU clocking which previously made it impossible to
actually set a clock that did not divide to a whole number (e.g.
150666666 Hz from the 452 MHz PFD2 parent clock).
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Enable CPU idle to be able to test the power management functionality.
Enable NEON to avoid crashing with our NEON enabled oe-core rootfs.
Enable the Asynchronous Sample Rate Converter (ASRC) which is actually
available on Vybrids.
Enable printk time now with the clock function being fixed thanks to
9195c464ad84836d85aa73aef384fe4382f7770d.
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Add initial Colibri VF50 support based off Timesys' implementation for
Freescale's Vybrid Tower System TWR-VF65GS10:
- New machine ID.
- FEC1 only.
- ESDHC2 only with card detect interrupt.
- PLL5 based RMII clocking (e.g. no external crystal).
- VESA VGA display timing (tested with 5.7" EDT ET057090DHU).
- Default UART_A on SCI0.
- UART_A and UART_C I/O muxing.
- I2C real time clock on carrier board.
- Early boot console support.
- 8-bit NAND.
Tested on early Colibri VF50 prototypes V1.0a mounting root file
systems both over NFS or from SD card ext3 partition.
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commit 55205c916e179e09773d98d290334d319f45ac6b upstream.
This change fixes a linking problem, which happens if oprofile
is selected to be compiled as built-in:
`oprofile_arch_exit' referenced in section `.init.text' of
arch/arm/oprofile/built-in.o: defined in discarded section
`.exit.text' of arch/arm/oprofile/built-in.o
The problem is appeared after commit 87121ca504, which
introduced oprofile_arch_exit() calls from __init function. Note
that the aforementioned commit has been backported to stable
branches, and the problem is known to be reproduced at least
with 3.0.13 and 3.1.5 kernels.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@nokia.com>
Signed-off-by: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: oprofile-list <oprofile-list@lists.sourceforge.net>
Link: http://lkml.kernel.org/r/20111222151540.GB16765@erda.amd.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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semaphore without requesting it
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cleanup debug comment / code in i2c-imx
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Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
with the memset return value. However the memset itself became broken
by that patch for misaligned pointers.
This fixes the above by branching over the entry code from the
misaligned fixup code to avoid reloading the original pointer.
Also, because the function entry alignment is wrong in the Thumb mode
compilation, that fixup code is moved to the end.
While at it, the entry instructions are slightly reworked to help dual
issue pipelines.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 418df63adac56841ef6b0f1fcf435bc64d4ed177)
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optimizations
Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on
assumptions about the implementation of memset and similar functions.
The current ARM optimized memset code does not return the value of
its first argument, as is usually expected from standard implementations.
For instance in the following function:
void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter)
{
memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter));
waiter->magic = waiter;
INIT_LIST_HEAD(&waiter->list);
}
compiled as:
800554d0 <debug_mutex_lock_common>:
800554d0: e92d4008 push {r3, lr}
800554d4: e1a00001 mov r0, r1
800554d8: e3a02010 mov r2, #16 ; 0x10
800554dc: e3a01011 mov r1, #17 ; 0x11
800554e0: eb04426e bl 80165ea0 <memset>
800554e4: e1a03000 mov r3, r0
800554e8: e583000c str r0, [r3, #12]
800554ec: e5830000 str r0, [r3]
800554f0: e5830004 str r0, [r3, #4]
800554f4: e8bd8008 pop {r3, pc}
GCC assumes memset returns the value of pointer 'waiter' in register r0; causing
register/memory corruptions.
This patch fixes the return value of the assembly version of memset.
It adds a 'mov' instruction and merges an additional load+store into
existing load/store instructions.
For ease of review, here is a breakdown of the patch into 4 simple steps:
Step 1
======
Perform the following substitutions:
ip -> r8, then
r0 -> ip,
and insert 'mov ip, r0' as the first statement of the function.
At this point, we have a memset() implementation returning the proper result,
but corrupting r8 on some paths (the ones that were using ip).
Step 2
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 1:
save r8:
- str lr, [sp, #-4]!
+ stmfd sp!, {r8, lr}
and restore r8 on both exit paths:
- ldmeqfd sp!, {pc} @ Now <64 bytes to go.
+ ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
(...)
tst r2, #16
stmneia ip!, {r1, r3, r8, lr}
- ldr lr, [sp], #4
+ ldmfd sp!, {r8, lr}
Step 3
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 0:
save r8:
- stmfd sp!, {r4-r7, lr}
+ stmfd sp!, {r4-r8, lr}
and restore r8 on both exit paths:
bgt 3b
- ldmeqfd sp!, {r4-r7, pc}
+ ldmeqfd sp!, {r4-r8, pc}
(...)
tst r2, #16
stmneia ip!, {r4-r7}
- ldmfd sp!, {r4-r7, lr}
+ ldmfd sp!, {r4-r8, lr}
Step 4
======
Rewrite register list "r4-r7, r8" as "r4-r8".
Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 455bd4c430b0c0a361f38e8658a0d6cb469942b5)
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This change fixes a linking problem, which happens if oprofile is selected to
be compiled as built-in:
`oprofile_arch_exit' referenced in section `.init.text' of
arch/arm/oprofile/built-in.o: defined in discarded section
`.exit.text' of arch/arm/oprofile/built-in.o
The problem is appeared after commit 87121ca504, which introduced
oprofile_arch_exit() calls from __init function. Note that the aforementioned
commit has been backported to stable branches, and the problem is known to be
reproduced at least with 3.0.13 and 3.1.5 kernels.
Cc: stable@kernel.org # 3.0+
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@nokia.com>
Signed-off-by: Robert Richter <robert.richter@amd.com>
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The issue was caused due to sched_clock() inplementation in pit.c which reported values which were incosistent with what it should
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default console (i.e. printf) for MQX as of the beta-3 release.
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routing interrupt routing bits unchanged
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Signed-off-by: Ed Nash <ed@kidlearn.com>
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manually integrate from the CAAM part by Jason
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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From Singh Pradip-B09147. Integrate by Jason Jin
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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Signed-off-by: Alison Wang <b18965@freescale.com>
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Add platform support for ADC driver.
Signed-off-by: Wang Xiaojun <b41435@freescale.com>
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Handle usb suspend/resume, currently the BSP doesn't
support usb plug/unplug wakeup.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
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