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2014-10-24ARM: dts: put the imx6sx-19x19-arm2-gpmi-weim.dts to the common dts dirrel_imx_3.10.31_1.1.0_beta2Jason Liu
put the imx6sx-19x19-arm2-gpmi-weim.dts to the common dts dir Signed-off-by: Jason Liu <r64343@freescale.com>
2014-10-23MLK-9732 ARM: dts: new dts supported NAND on i.MX6SX 19x19 ARM2 boardAllen Xu
supported NAND on i.MX6SX 19x19 ARM2 board. Signed-off-by: Allen Xu <b45815@freescale.com>
2014-10-14Revert "ARM: imx: fix .is_enabled() of shared gate clock"Jason Liu
This reverts commit 920fa48dd74b158e8a359cc546cf9f6cbfcd95a9. [Beta2 release does not include Bug fix patches] Signed-off-by: Jason Liu <r64343@freescale.com>
2014-10-13MLK-9675 ARM: dts: code change for new QSPI chip on SDB boardAllen Xu
QSPI chip changed from spansion s25fl128s to micron n25q256a Signed-off-by: Allen Xu <b45815@freescale.com>
2014-10-13MLK-9634-1 arm: imx: remove romcp workaround for i.mx6sx TO1.2Anson Huang
i.MX6SX TO1.2 ROM has add ocram_s space support for ARM resume, so no need to enable ROMCP to workaround it for TO1.2. Signed-off-by: Anson Huang <b20788@freescale.com>
2014-10-09MLK-9641: ARM: dts: imx6sx-sdb: change pfuze100 to pfuze200 on RevB boardRobin Gong
On imx6sx-sdb-revb board we use pfuze200 and pfuze100 on reva board. Signed-off-by: Robin Gong <b38343@freescale.com>
2014-09-29ARM: imx: fix .is_enabled() of shared gate clockShawn Guo
Commit 63288b721a80 ("ARM: imx: fix shared gate clock") attempted to fix an issue with particular enable/disable sequence from two shared gate clocks. But unfortunately, while it partially fixed the issue, it also did something wrong in .is_enabled() function hook. In case of shared gate, the function shouldn't really query the hardware state via share_count, because the function is trying to query the enabling state of the clock in question, not the hardware state which is shared by multiple clocks. Fix the issue by returning the enable_count of the clock itself which is maintained by clock core, in case it's a clock sharing hardware gate with others. As the result, the initialization of share_count per hardware state is not needed now. So remove it. shawn.guo: cherry-pick commit 9e1ac462b982 from upstream Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Fixes: 63288b721a80 ("ARM: imx: fix shared gate clock") Cc: <stable@vger.kernel.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-25ENGR00333130-2 dts: imx6sx: add legacy imx6sx sdb revA supportDong Aisheng
The CAN transceiver is changed on RevB board and the default imx6sx-sdb.dts is for support new RevB board. This patch adds the dts for legacy RevA board support, especially for CAN device. This is for people who still wants to use RevA board with this code base. Signed-off-by: Dong Aisheng <b29396@freescale.com>
2014-09-25ENGR00333130-1 ARM: imx6sx: setting can trx according to gpio flagsDong Aisheng
With this, we can pass the gpio active flag from device tree for initialize the transceiver. Signed-off-by: Dong Aisheng <b29396@freescale.com>
2014-08-05ENGR00242201 imx: Update specific clock code for MX6DLLoren Huang
-Update the parent of gpu2d_core for mx6dl. -Update the parent of gpu3d_shader and gpu3d_core for mx6dl. -Update the clock of gpu3d_shader and gpu3d_core for mx6dl. The code change is cherry-picked from patch 00e75bcba16d. Signed-off-by: Loren Huang <b02279@freescale.com> (cherry picked from commit 2b335e6232b807d114a5a57e0b5956ab794786a4)
2014-07-21ENGR00323924 iMX6SX: dts: disable weim-nor in default dtsAllen Xu
only enable this module in specific dts file. Signed-off-by: Allen Xu <b45815@freescale.com>
2014-07-21ENGR00323464 ARM: dts: imx6sx: add gpmi-weim dts fileAllen Xu
Add new dts file and enable gpmi module. Signed-off-by: Allen Xu <b45815@freescale.com>
2014-07-17ENGR00323027 MTD:QuadSPI: Remove the M4 checking workaroundYe.Li
The QuadSPI driver has a workaround to check if M4 is using QuadSPI NOR flash. When M4 is running on QuadSPI NOR, the QuadSPI driver will quit. This workaround has a bug when system booting from QuadSPI NOR. Therefore, removed the workaround and disabled the QuadSPI driver in MCC specific DTB. The MCC DTB will let the QuadSPI driver to disabled, not conflict with M4. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 6733ca3382ddb6358f4ccf8dd4f16d8f65995241)
2014-07-17ENGR00323026 iMX6SX:MCC Disable ADC1 and ADC2 in MCC DTSYe.Li
M4 has occupied the ADC1 and ADC2 in RDC, must disable them in DTS to avoid kernel boot panic. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 046b1c214af6740e7936aae6876941e79c10da8e)
2014-07-16ENGR00323074 ARM: dts: imx6sx-sdb: add v4l2 capture and csi node for vadcRobby Cai
enable dual camera support on imx6sx-sdb. For camera ov5640, need an adapter (sch 700-28342) For VADC, need expansion board (sch 700-26109) Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Robby Cai <r63905@freescale.com> (cherry picked from commit ce4e36b59f225b3af75ba04accde746049a58cb4)
2014-07-15ENGR00322509-2 ARM:imx6sl:busfreq: Fix incorrect clk_set_parent() call.Ranjani Vaidyanathan
The code incorrectly attempts to set the parent of periph2_clk to periph2_clk2_sel. Fix this by calling the clk_set_parent() function with the correct parameters. Also replace all calls to clk_set_parent() and clk_set_rate() with imx_clk_set_parent() and imx_clk_set_rate() function that prints out error messages in case of failure. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
2014-07-15ENGR00322509-1 Revert "ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag ↵Ranjani Vaidyanathan
for PLL clocks" The commit aabf4911f9971d4a6f02fe74bfdd39e7d74b7154, which added a check to prevent pll rate changes when PLL is enabled, causes incorrect reporting of MMDC clock during low power IDLE. So revert the patch as the code needs to be improved to handle all cases. Revert "ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocks" This reverts commit aabf4911f9971d4a6f02fe74bfdd39e7d74b7154. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
2014-07-15ENGR00318063-11: ARM: imx6: add return check for clock callsShawn Guo
There are a bunch of clk_enable_prepare, clk_set_parent and clk_set_rate calls in imx6 clock driver's initialization. They are called without retunr check. If there is something going wrong with the calls, they will just fail silently. The patch creates a set of helper functions imx_clk_enable_prepare, imx_clk_set_parent and imx_clk_set_rate, and use them instead from clock initialization to check the return and print error message to tell failures if any. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-15ENGR00322895 dts: imx6sx-sdb: config PAD setting for GPIO17Shengjiu Wang
GPIO17 is used by headphone jack. if don't config the PAD setting, the gpio value is not correct. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
2014-07-15ENGR00322015 dts: imx6qdl: dcic: set dcic1 as disp-axi clock for dcic2Sandor Yu
On imx6dl dcic2 clock gate depend on dcic1, so setting dcic1 as disp-axi clock for dcic2 in imx6qdl dts. Signed-off-by: Sandor Yu <R01008@freescale.com>
2014-07-14ENGR00322563 ARM:imx6sl:Ensure that the CPU frequency is maintianed at ↵Ranjani Vaidyanathan
396MHz in low power idle. In low power IDLE mode, CPU needs to be sourced from PLL1 instead of PLL2_PFD0 as PLL2 needs to be in bypass mode to achieve 24MHz DDR frequency. The original code attempts to relock the PLL1 at frequency that is as close as possible to 396MHz, which results in PLL1 at 648MHz and the ARM freq turns out to be 324MHz instead of 396MHz. This causes issues with CPUFREQ as 324MHz is not a frequency listed in the cpufreq table in the device tree. This patch attempts to fix this mis-match and maintains CPU freq at 396MHz in low power idle. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
2014-07-11ENGR00322272-1: ARM: imx6sx: hide the buggy ldb_di_sel mux from clk APIShawn Guo
This is a smilar change for imx6sx clock tree as what we did for imx6q with commit 0bec46131d88 (ENGR00318063-8: ARM: imx6q: hide buggy ldb_di_sel from clk API). As the valid procedure of switching ldb_di_sel on imx6sx is not available yet, we hide this buggy mux by looking at the parent selection done by bootloader and register it statically to clock framework, so that switching this buggy mux becomes impossible. Also, since the bit width of ldb_di_sels is 3, we add two "dummy" entries for ldb_di_sels to avoid out-of-bounds error. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-09ARM: imx: fix shared gate clockShawn Guo
Let's say clock A and B are two gate clocks that share the same register bit in hardware. Therefore they are registered as shared gate clocks with imx_clk_gate2_shared(). In a scenario that only clock A is enabled by clk_enable(A) while B is not used, the shared gate will be unexpectedly disabled in hardware. It happens because clk_enable(A) increments the share_count from 0 to 1, while clock B is unused to clock core, and therefore the core function will just disable B by calling clk->ops->disable() directly. The consequence of that call is share_count is decremented to 0 and the gate is disabled in hardware, even though clock A is still in use. The patch fixes the issue by initializing the share_count per hardware state and returns enable state per share_count from .is_enabled() hook, in case it's a shared gate. While at it, add a check in clk_gate2_disable() to ensure it's never called with a zero share_count. Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Fixes: f9f28cdf2167 ("ARM: imx: add shared gate clock support") Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-04ENGR00321358-2 dts: imx6sx: change m_can message ram to a small sizeDong Aisheng
We met an issue that access the 0x2600 offset of message ram does not work although the mx6sx spec claims a 16KB size. The reason is still unkown. Change the RAM size to a small size to use the first 2K to avoid such issue. Signed-off-by: Dong Aisheng <b29396@freescale.com>
2014-07-04ENGR00321308 ARM: imx: make sure OCOTP clk is enabled in MSLAnson Huang
As some modules need to access ocotp in MSL, so we need to make sure it is enabled during MSL, after kernel boot up, clk dirver will disable it in late init. Signed-off-by: Anson Huang <b20788@freescale.com>
2014-07-04ENGR00321288 ARM: imx: gpc: fix VADC power off while pu management activeRobin Gong
bit17/bit18 of GPC_CNTR worked as VADC power state control, that's function looks different with other bits of this register: write 1 raise power request and write 0 do nothing. Need read and write only the related bit fields of the register to avoid touch bit17/bit18 on i.mx6sx. Also fix the same for pcie power on/off. Signed-off-by: Robin Gong <b38343@freescale.com>
2014-07-04ENGR00320383-2 ARM: imx: fix random failure for ddr3 freq scaling on i.mx6sxAnson Huang
Improve DDR3 freq scaling procedure of i.MX6SX: 1. some code of condition check is incorrect; 2. better to keep MMDC command same as ddr script; 3. improve the clock tree change of mmdc path; 4. remove precharge command. Signed-off-by: Anson Huang <b20788@freescale.com>
2014-07-04ENGR00320383-1 ARM: imx: correct ddr3 busfreq change flow of i.mx6sxAnson Huang
Now that we have found the root cause of ddr3 freq scaling of i.MX6SX, we can remove the previous workaround and add correct fix. Revert "ENGR00316496 ARM: imx: fix random failure for ddr3 freq scaling on i.mx6sx" This reverts commit 93510bfa720670b2f80a7f35ffb327f69fcb0f21. Signed-off-by: Anson Huang <b20788@freescale.com>
2014-07-03ENGR00321114 dts: Recpvery gpr item in vadc dts itemSandor Yu
Gpr item is remove from vadc dts by dcic patch incorrectly. It should add back, otherwise vadc driver can not initialized. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit f24c5f76c18745c3b6b7562a873dedf0d4a3c321)
2014-07-03ENGR00317086-5 dts: Enable dcic driver for imx6sxSandor Yu
Enable dcic driver for imx6sx ARM2 and SDB board. Setting LCDIF pins bit 4 for loopback to dcic. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit bf508e6be22d077043c071477250e208621aefd2)
2014-07-03ENGR00317086-4 dts: Enable dcic driver for imx6q/dlSandor Yu
Enable dcic driver for imx6q/dl SabreSD and SabreAI Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit eec9deb496b20e9dba0de071da9fdfdf779895b3)
2014-07-03ENGR00317086-3 dcic: Add dcic driver source codeSandor Yu
Add dcic driver source code. Support two instance dcic1 and dcic2. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit 5dd90299f33e93252bd1cc7a9704adb9f469fa66)
2014-07-03ENGR00317086-1 clk: Add dcic clock define for imx6qSandor Yu
Add dcic1 and dcic define in imx6q clock tree. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit 93ae4ba005f1931ed3cd4e0ac0e8948e3752ad68)
2014-07-02ENGR00320554: ARM: imx: drop unncessary PL310 errataRichard Liu
The PL310 integrated on i.MX6 series and VF610 are revision r3p1 and later. Per ARM PL310 errata document, 588369 is fixed in r2p0 and 727915 is fixed in r3p1. Neither is needed for i.MX6 or VF610. So let's drop them. Signed-off-by: Richard Liu <r66033@freescale.com> Acked-by: Jason Liu <r64343@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-02ENGR00320692-2 ARM: dts: imx6sl: make an alias for csiRobby Cai
Becuase in fsl_csi.c, there's a function call as follows. id = of_alias_get_id(pdev->dev.of_node, "csi"); The corresponding change has been made for imx6sx, but not for imx6sl. This patch fixed it by making an alias csi0. Signed-off-by: Robby Cai <r63905@freescale.com> (cherry picked from commit a5738d856fd5a8176f04a5eb316dfd512603ab4a)
2014-07-02ENGR00320692-1 ARM: dts: imx6sl: fix "csi_id is missing or invalid" issueRobby Cai
csi_id property is missing in dts file for imx6sl-evk board, which causes the following kernel dump when insert the csi_v4l2_capture module. This patch fixed it. csi_v4l2 csi_v4l2_cap.22: csi_id missing or invalid Unable to handle kernel NULL pointer dereference at virtual address 00000034 pgd = a8774000 [00000034] *pgd=a957f831, *pte=00000000, *ppte=00000000 Internal error: Oops: 817 [#1] PREEMPT SMP ARM Modules linked in: csi_v4l2_capture(+) fsl_csi ov5642_camera ov5640_camera evbug CPU: 0 PID: 829 Comm: modprobe Not tainted 3.10.31-1.1.0_beta+g3c16fd0 #1 task: a881ef00 ti: a892c000 task.ti: a892c000 PC is at csi_v4l2_probe+0x2a0/0x35c [csi_v4l2_capture] LR is at csi_v4l2_probe+0x290/0x35c [csi_v4l2_capture] Signed-off-by: Robby Cai <r63905@freescale.com> (cherry picked from commit d0173b8ba4027983b2b9e988fafb64124ccb9731)
2014-06-30ENGR00320428 v4l2 capture: imx6sx: fix "csi_id is missing or invalid" issueRobby Cai
csi_id property is missing in dts file for imx6sx-sdb board, which causes the following kernel dump when insert the csi_v4l2_capture module. This patch fixed it. udevd[122]: starting version 182 csi_v4l2 csi1_v4l2_cap.29: csi_id missing or invalid Unable to handle kernel NULL pointer dereference at virtual address 00000034 pgd = a8c50000 [00000034] *pgd=a8c2f831, *pte=00000000, *ppte=00000000 Internal error: Oops: 817 [#1] PREEMPT SMP ARM Modules linked in: evbug csi_v4l2_capture(+) fsl_csi CPU: 0 PID: 147 Comm: udevd Not tainted 3.10.31-01988-gd965cfd-dirty #831 task: a8c95a40 ti: a8c4c000 task.ti: a8c4c000 PC is at csi_v4l2_probe+0x58/0xfc [csi_v4l2_capture] LR is at csi_v4l2_probe+0x50/0xfc [csi_v4l2_capture] pc : [<7f007efc>] lr : [<7f007ef4>] psr: a00f0113 sp : a8c4de40 ip : 600f0113 fp : 00097220 r10: 7f00c000 r9 : a8c4c000 r8 : 7f009d78 r7 : 00000000 r6 : a80ec810 r5 : a80ec800 r4 : 7f009f30 r3 : a8c03000 r2 : 00000000 r1 : a8c03000 r0 : 00000000 Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user Control: 10c53c7d Table: a8c5004a DAC: 00000015 Process udevd (pid: 147, stack limit = 0xa8c4c238) Stack: (0xa8c4de40 to 0xa8c4e000) This patch also changed csi_id for vadc to 1. Signed-off-by: Robby Cai <r63905@freescale.com>
2014-06-30ENGR00320355 dts: imx6: mmc index fixed by controller orderDong Aisheng
Make the linux mmc index to be fixed according to controller order. This can make user easily to identify which mmcX corresponding to which controller and kernel be able find the rootfs in a card plugged in a specific slot persistently. This is a eventually solution for finding mmc block devices correctly for different cards on multi slots. Signed-off-by: Dong Aisheng <b29396@freescale.com> (cherry picked from commit d6aa7401f65fbe5458e5459526d84405fdf4d078)
2014-06-29ENGR00320056-4 ARM: dts: imx6sx-19x19-arm2: Add CSI2 supportRobby Cai
Add CSI2 support. use CSI2 for VADC instead of CSI1. Signed-off-by: Robby Cai <r63905@freescale.com> (cherry picked from commit 9de447e3c715fa570c145bdd2e9692f59b0072a3)
2014-06-29ENGR00320056-3 ARM: dts: imx6sx: make the alias for two CSIsRobby Cai
make the alias for two CSI ports. Signed-off-by: Robby Cai <r63905@freescale.com> (cherry picked from commit 3ba09b29305103b466cc4afa038df9b77818d3c5)
2014-06-27ENGR00320205 dts: imx6sx-sdb: Support spdif out in sx-sdb boardShengjiu Wang
Add device tree for spdif in sx-sdb board. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
2014-06-27ENGR00318063-10: ARM: imx6qdl: update mmdc_ch0_axi name in mux selectionsShawn Guo
Commit ac166cffc9de (ENGR00318063-7: ARM: imx6q: mmdc_ch_axi clock should be non-gateable) dropped the non-exist gate clock mmdc_ch0_axi by pointing it to mmdc_ch0_axi_podf. But it forgot updating clock name used in clock mux selections. This causes call like clk_set_parent(clk[gpu3d_core_sel], clk[mmdc_ch0_axi]) to fail. Fix the failure by updating clock name in mux selections to be "mmdc_ch0_axi_podf". Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-06-27ENGR00320108 ARM: imx6sx-sdb: enable usb charger detectionPeter Chen
Enable SoC usb charger detect function Signed-off-by: Peter Chen <peter.chen@freescale.com>
2014-06-27ENGR00320185-2 IMX6SX/DISPMIX: add dispmix on/off support for 6SX platformFancy Fang
Modify the dispmix on/off interfaces to add specific support for 6sx platform. Signed-off-by: Fancy Fang <chen.fang@freescale.com> (cherry picked from commit 31aab0b205ea9438de96f04ac0201c6fec3a669c)
2014-06-27ENGR00320185-1 IMX6SX/DISPMIX: add dispmix on/off support for 6SX platformFancy Fang
Add the required clocks for the dispmix on/off operation. This include clocks definition and initialization. Signed-off-by: Fancy Fang <chen.fang@freescale.com> (cherry picked from commit 638acb3c30b135901631e59c9938e06422cc4b76)
2014-06-27ENGR00320101 dts: imx6sx: Update the mma8451 device tree to add interrupt ↵luweizhou
mode option. The driver for android team need to enalbe mma8451 fifo overflow interrupt feather. So add the interrupt option into device tree. Signed-off-by: Luwei Zhou <b45643@freescale.com> (cherry picked from commit 443fd43f454215f615ee326ddb02911e05bcd2ae)
2014-06-26Revert "ENGR00318063-5: ARM: imx: set CLK_SET_PARENT_GATE flag for glitchy ↵Shawn Guo
mux clocks" This reverts commit cf56832a5ddf3a7caf3641bc272f59c7033f0b88. The change has a much bigger impact than we initially thought. It basically requires client drivers to check return of every single clk_set_parent() and clk_set_rate() call to know if they're doing something that clock driver prohibits for sake of glitch. The client drivers haven't been so ready for this change, so let's revert it from release branch and keep developing it on main branch for a while. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-06-26ENGR00320088 ARM: imx: disable Mega/Fast mix off featureAnson Huang
As some modules in M/F domain are not ready for this feature, so need to disable it until every driver are ready for it. Signed-off-by: Anson Huang <b20788@freescale.com>
2014-06-26ENGR00319792 ARM: imx: need to make sure MMDC auto self refresh is enabledAnson Huang
When there is busfreq scaling between low power mode and audio bus mode, the enabling of MMDC auto self-refresh code will be skipped as they are both DLL off mode, it will cause DDR power increase, so we just move the enabling of the MMDC auto self-refresh mode to the end of busfreq change to make sure it is enabled after a DDR freq change. Signed-off-by: Anson Huang <b20788@freescale.com>
2014-06-26ENGR00316496 ARM: imx: fix random failure for ddr3 freq scaling on i.mx6sxAnson Huang
Improve DDR3 freq scaling procedure of i.MX6SX: 1. some code of condition check is incorrect; 2. better to keep MMDC command same as ddr script; 3. improve the clock tree change of mmdc path; 4. remove CON_REG req for MMDC. Signed-off-by: Anson Huang <b20788@freescale.com>
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