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As DDR freq change is by modifying CCM register directly,
we need to update the clock tree as well, or the clock
tree will be broken. Also, we need to make sure the clock
rate counting is right.
Signed-off-by: Anson Huang <b20788@freescale.com>
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There is no fuse data for distinguish 1.2G or 1G, kernel need support passed
param from u-boot that can know 1.2G or 1G. If 1.2G, will configure VDDSOC_IN
&VDDARM_IN to 1.425V by pfuze and VDDSOC&VDDPU to 1.25V by internal ldo
Signed-off-by: Robin Gong <B38343@freescale.com>
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If the CPUFreq change is done before enabling low bus freq driver,
the bus freq will be staying at high freq until there is new request
of entering low bus freq. So we need to put the bus freq into low
point if all the conditions are met when we enable bus freq.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The max freq for IPU and AXI clocks is 264MHz. Hence source
IPU from mmdc_ch0 clock on MX6 to get maximum frequency.
And source AXI from periph_clk on for max freq.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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According to ticket TKT094250 :There is no VBUS supply or not supply for USB
PHY power 3p0,USB dp/dm is floating when there is no connection in device mode:
S/W can run the following flow to ensure the internal DP/DM linestate does not
change. These should be done before set SUSP/PHCD bit after detecting the VBUS
change from high to low.
clear HW_USBPHY_DEBUG_CLKGATE
loopback_utmi_dig_tst1 = 1
loopback_utmi_dig_tst0 = 0
loopback_tsti_tx_en = 1
loopback_tsti_tx_hiz = 0
loopback_tsti_tx_hs_mode = 0;
After detecting the VBUS or ID change (connected to a host or device), SW do:
set HW_USBPHY_DEBUG_CLKGATE back to 1
clear the loopback_XXXX signals above back to 0
Signed-off-by: make shi <b15407@freescale.com>
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only set board-specific data and re-use the existing SPI-NOR
flash driver.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Add usb charger support for i.mx6
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Store anatop base address at udc's platform data for i.mx6x
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Add thermal driver device to support thermal driver interface,
but as this driver is dependent on OCOTP driver and need a
calibrated part, so the temp read from the thermal sysfs
interface maybe inaccurate on those uncalibrated parts.
Signed-off-by: Anson Huang <b20788@freescale.com>
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fix a type: It should be "#if", not "#ifdef".
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Need to make sure gpt serial clock enabled on Arik TO1.0.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The default .config defines the GPU as a module:
"CONFIG_MXC_GPU_VIV=m"
In this case, we actually can not find the CONFIG_MXC_GPU_VIV.
We should find CONFIG_MXC_GPU_VIV_MODULE instead.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Ensure that the CPUFREQ driver sets the CPU to its maximum
frequency when it is suspended.
Also change the WAIT macro in clock.c to use GPT counter
for the delay instead of getnsdayoftime(). As the kernel
timekeeping driver is suspended before CPUFREQ and this
causes a dump during suspend.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Currently caam is not selected by default.
For test requirement, we need to set it to be built as module.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Need to update loops_per_jiffy when cpufreq is changed, our platform
only change the loops_per_jiffy of per_cpu cpu_data, we need to update
it to global loops_per_jiffy which is used for udelay, this is for pure
cpu freq change.
Signed-off-by: Anson Huang <b20788@freescale.com>
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- For the system dump issue of usb unhandled irq,
the root cause is the shared resource being lack of protection
add mutex to protect the shared access.
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
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enhance drive strength of sd pad ctrl to 40ohm otherwise it
will report error while trying to communicate with atheros
wifi.
error message looks like:
- "mmc2: error -84 whilst initialising SDIO card"
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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1. no vmmc regulator device was registered.
2. move initialization of usdhc into mx6_arm2_init.
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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Add HDMI register define in HDMI register head file
Signed-off-by: Sandor Yu <R01008@freescale.com>
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As SOC team suggestion, we should change VDDCORE from 1.1V to 1.05V at 672Mhz
Signed-off-by: Robin Gong <B38343@freescale.com>
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1. When resume, we can enable I cache and branch prediction
early to speed up the resume process;
2. L2 cache still need clean before suspend to make suspend/resume
modifiedre stable, add it back until we find the root cause.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add vivante drm modules code and select it in default config. Integrate
these code from vivante.
Signed-off-by: Allen Xu <allen.xu@freescale.com>
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Previous patch only check the condition that GPT broadcast
event is ready or not before doing clock event switch.
It's not enough, as the clock switch from local timer to GPT
broadcast must be happen after GPT broadcast clock event setup
and current cpu's clock device switch to local timer clock event.
Otherwise, we will have chance that cpu exit the wait mode and
switch back clock event without local timer event setup correctly.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Register watchdog platform device and re-use watchdog driver.
Signed-off-by: Robby Cai <R63905@freescale.com>
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If miss to configure IRQ for max11801, the max11801 driver fails to
probe and returns error,sabresd battery driver also fails to sample
voltage by max11801 ADC.
Signed-off-by: Rong Dian <b38775@freescale.com>
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registered viim platform divice.
Signed-off-by: Robby Cai <R63905@freescale.com>
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When we kill a secondary cpu, we need to wait for it
die, then kill it from hardware setting. And to avoid
the cache unalign issue, we use hardware register to
send flag to inform main cpu to kill secondary cpu.
Signed-off-by: Anson Huang <b20788@freescale.com>
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During booting of cpu1, there is a short window where cpu1
is online, but not active where cpu1 is occupied by waiting
to become active. If cpu0 then decides to schedule something
on cpu1 and wait for it to complete, before cpu0 has set
cpu1 active, we have a deadlock.
Typically it's this CPU frequency transition that happens at
this time, so let's just not wait for it to happen, it will
happen whenever the CPU eventually comes online instead.
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: stable@kernel.org
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Reviewed-by: Rickard Andersson <rickard.andersson@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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When a CPU is hotplugged off, we migrate any IRQs currently affine to it
away and onto another online CPU by calling the irq_set_affinity
function of the relevant interrupt controller chip. This function
returns either IRQ_SET_MASK_OK or IRQ_SET_MASK_OK_NOCOPY, to indicate
whether irq_data.affinity was updated.
If we are forcefully migrating an interrupt (because the affinity mask
no longer identifies any online CPUs) then we should update the IRQ
affinity mask to reflect the new CPU set. Failure to do so can
potentially leave /proc/irq/n/smp_affinity identifying only offline
CPUs, which may confuse userspace IRQ balancing daemons.
This patch updates migrate_one_irq to copy the affinity mask when
the interrupt chip returns IRQ_SET_MASK_OK after forcefully changing the
affinity of an interrupt.
Cc: stable@vger.kernel.org
Reported-by: Leif Lindholm <leif.lindholm@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ARM unconditionally selects CONFIG_GENERIC_HARDIRQS, so the definition
of for_each_irq_desc will check that the desc is non-NULL anyway.
This patch removes a redundant check from the IRQ migration code.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Our selection of interrupts to consider for IRQ migration is sub-
standard. We were potentially including per-CPU interrupts in our
migration strategy, but omitting chained interrupts. This caused
some interrupts to remain on a downed CPU.
We were also trying to migrate interrupts which were not migratable,
resulting in an OOPS.
Instead, iterate over all interrupts, skipping per-CPU interrupts
or interrupts whose affinity does not include the downed CPU, and
attempt to set the affinity for every one else if their chip
implements irq_set_affinity().
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Now that the GIC takes care of selecting a target interrupt from the
affinity mask, we don't need all this complexity in the core code
anymore. Just detect when we need to break affinity.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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irqdesc's node member is supposed to mark the numa node number for the
interrupt. Our use of it is non-standard. Remove this, replacing the
functionality with a test of the affinity mask.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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On Mon, Jul 11, 2011 at 3:52 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
...
> The __exception annotation on a function causes this to happen:
>
> [<c002406c>] (asm_do_IRQ+0x6c/0x8c) from [<c0024b84>]
> (__irq_svc+0x44/0xcc)
> Exception stack(0xc3897c78 to 0xc3897cc0)
> 7c60: 4022d320 4022e000
> 7c80: 08000075 00001000 c32273c0 c03ce1c0 c2b49b78 4022d000 c2b420b4 00000001
> 7ca0: 00000000 c3897cfc 00000000 c3897cc0 c00afc54 c002edd8 00000013 ffffffff
>
> Where that stack dump represents the pt_regs for the exception which
> happened. Any function found in while unwinding will cause this to
> be printed.
>
> If you insert a C function between the IRQ assembly and asm_do_IRQ,
> the
> dump you get from asm_do_IRQ will be the stack for your function,
> not
> the pt_regs. That makes the feature useless.
>
When __irq_svc - or any of the other exception handling assembly code -
calls the C code, the stack pointer will be pointing at the pt_regs
structure.
All the entry points into C code from the exception handling code are
marked with __exception or __exception_irq_enter to indicate that they
are one of the functions which has pt_regs above them.
Normally, when you've entered asm_do_IRQ() you will have this stack
layout (higher address towards top):
pt_regs
asm_do_IRQ frame
If you insert a C function between the exception assembly code and
asm_do_IRQ, you end up with this stack layout instead:
pt_regs
your function frame
asm_do_IRQ frame
This means when we unwind, we'll get to asm_do_IRQ, and rather than
dumping out the pt_regs, we'll dump out your functions stack frame
instead, because that's what is above the asm_do_IRQ stack frame
rather than the expected pt_regs structure.
The fix is to introduce handle_IRQ() for no exception stack dump, so
it can be called with MULTI_IRQ_HANDLER is selected and a C function
is between the assembly code and the actual IRQ handling code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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Rather than open-coding the jiffy-based wait, and polling for the
secondary CPU to come online, use a completion instead. This
removes the need to poll, instead we will be notified when the
secondary CPU has initialized.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Sourcing AXI_CLK from PLL3_PFD_540M causes the system to
hang on resuming from STOP mode.
The main issue is that PFDs may sometimes hang/freeze
when their parent PLLs are powered on and then relocked
when exiting from STOP mode. To avoid this, PFDs must
be disabled before entering STOP and enabled after resume.
The fix is to move axi_clk to periph_clk before system
enters STOP and then restore it back to PLL3_PFD_540M
after resume.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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We need to turn of cache coherency of secondary core before
it is disable by core0, otherwise, the secondary core may be
waked by cache sync, and if it exit from wfi and access BUS,
meanwhile, core0 disable it from hardware, the whole SOC would
hang.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Its similar to ENGR00178581.
Remove call to regulator_has_full_constraints() from Max17135 EPD PMIC
initialization code, since leaving it enabled results in a failure of
system to load properly - key regulators are disabled when 'epdc' is added
to the kernel command line.
Signed-off-by: Robby Cai <R63905@freescale.com>
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- Remove configuration of PWM1 pad for EPDC. Was there for debug purposes,
but caused problems with LCD support.
Signed-off-by: Danny Nold <dannynold@freescale.com>
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Add Sipix panel option in imx6s_defconfig file
Signed-off-by: Fugang Duan <B38611@freescale.com>
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- Add IOMUX pad config defines and GPIO defines
- Add platform device/data for SPDC
- Add IRQ number define for SPDC
Signed-off-by: Fugang Duan <B38611@freescale.com>
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- remove repeated ePXP device register.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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check CONFIG_ARCH_MX6 to replace cpu type
Signed-off-by: Gary Zhang <b13634@freescale.com>
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operate WM8962 MCLK by callback
Signed-off-by: Gary Zhang <b13634@freescale.com>
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add wm8962 codec support for mx6sl arm2
Signed-off-by: Gary Zhang <b13634@freescale.com>
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dual camera support for mx6q and mx6dl:
1. let mipi and parallel camera working on different csi
2. the two camera can work independently and synchronously
3. the two camera will be registered and different video
device(/dev/video0, /dev/video1)
4. when both camera are working, the can not use the same
ipu channel, that is, when camera one using PRP_ENC_MEM
or PRP_VF_MEM channel, the other one can only use CSI_MEM
this is the arch part changes.
Signed-off-by: Wu Guoxing <b39297@freescale.com>
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As Mx6 dq, dl and sl have different DDR IO address, so
we need to do the DDR IO low power setting according
to different CPU type.
Also, Mx6sl has some different config in DSM, need to
separate it from other platforms.
Change mx6q_suspend to mx6_suspend, as it is a common
thing for all mx6 platforms.
Add rtc driver for mxsl platform to support suspend/resume test.
Signed-off-by: Anson Huang <b20788@freescale.com>
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DLL ON/OFF code randomly hangs waiting for the CON_ACK bit
to be set when a CON_REQ is asserted.
Fix this by adding a delay after the MMDC automatic power savings
mode is disabled.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add support DVFS-CORE to MX6Sololite.
Set PLL1 in bypass mode when ARM freq drops below 400MHz.
ARM will be sourced from PLL2_PFD2_400M in this case.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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To avoid the ARM from accepting an interrupt in the dangerous
window, reduce the ARM core freq just before the sytem is
about to enter WAIT state.
Reduce the ARM freq so as to maintain 12:5 ARM_CLK to IPG
ratio. Use the ARM_PODF to drop the frequency.
In a multicore case the frequency is dropped only when all the
4 cores are going to be in WFI.
In case of single core environment, its easy to drop the ARM core
freq just before WFI since there is no need to identify the state of
the other cores.
Some other points to note:
1. If "mem_clk_on" is added to the command line, the memory clocks will
not be gated in WAIT mode. This will increase the system IDLE power.
This mode is valid only on MX6sl, MX6DQ TO1.2 and MX6DL TO1.1.
2. In case the IPG clk is too low (for ex 50MHz) and ARM is at 1GHz,
we cannot match the 12:5 ratio using ARM_PODF only. In this case,
donot clock gate the memories in WAIT mode (available on MX6SL,
MXDQ TO1.2 and MXDL TO1.1). For MXDQ TO1.1 and MX6DL TO1.0, disable
system wide WAIT entry in this case.
In STOP mode, always ensure that the memory clocks are gated, else
power impact will be significant.
WAIT mode is enabled by default with this commit.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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