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Conflicts:
drivers/input/touchscreen/egalax_ts.c
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Fix Mux config
Need hardware rework:
1. Add R450 10.0k
2. Remove R1105 1k
3. short Pin 1,2 of u516: will impact CAN1
Signed-off-by: Hake Huang <b20222@freescale.com>
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This issue will happen only when suspend bit is set but phcd is not set
The root cause of this issue is the IC defect.
- If the suspend bit is set without phcd bit set, host controller
can't resume normally
- The workaround is after set suspend bit, we need set the following
bit in USB PHY at once:
HW_USBPHY_PWD_RXPWDRX
HW_USBPHY_PWD_RXPWDDIFF
HW_USBPHY_PWD_RXPWD1PT1
HW_USBPHY_PWD_RXPWDENV
HW_USBPHY_PWD_TXPWDv2I
HW_USBPHY_PWD_TXPWDIBIAS
HW_USBPHY_PWD_TXPWDFS
- Furthermore, after resume, we must clear these bits during the K state
- IC has no plan to fix this issue
- This issue only happen on MX6Q/MX28
MSL part
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
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This commit mainly build in GPIO keypad.But because config
file have not been update for long time, some item is added
by kconfig automatically.
The step is make imx6_defconfig,
Make menuconfig,
Choose gpio keypad enable
Cp .config to imx6_defconfig
Signed-off-by:Yuxi Sun <b36102@freescale.com>
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As there might be dirty data line on any core of MX6
SOC when power on or reset, we need to do L1 I-cache
invalidation in the resume process and start up
process for all cores.
This is very important for us, as not all of the hardware
will do cache invalidation during power on or reset, so
we need to do the invalidation for all cache(L1, L2,
I and D) before first time enabling. Please keep in mind.
Signed-off-by: Anson Huang <b20788@freescale.com>
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We have many operation before enabling L2 cache, which can
make sure L2 already can be accessed before enabled.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Conflicts:
arch/arm/mach-mx6/board-mx6q_arm2.c
arch/arm/mach-mx6/board-mx6q_sabrelite.c
arch/arm/plat-mxc/dvfs_core.c
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GPU pmem is used by video surface buffer, which must be
non cachable.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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fix the board level function
Signed-off-by: Robin Gong <B38343@freescale.com>
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Fix the following build warning:
1.arch/arm/mach-mx6/cpu.c:36: warning: function declaration isn't a
prototype
2.arch/arm/mach-mx6/system.c:55: warning: function declaration isn't a
prototype
3.arch/arm/mach-mx6/board-mx6q_sabreauto.c:751: warning: unused variable
'iterations'
Signed-off-by: Anson Huang <b20788@freescale.com>
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Fix HDMI AVI info frame config register bit define error.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Set ov5640 as the default camera
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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in __clk_disable, check usecount, if it is 0, return, otherwise,
the usecount will be un-correct.
Signed-off-by: Wu Guoxing <b39297@freescale.com>
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Add board level code for mlb, including platform data, clock, etc.
Signed-off-by: Terry Lv <r65388@freescale.com>
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OV8820 MIPI camera driver will be built as a module default.
Signed-off-by: Even Xu <b21019@freescale.com>
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Add usb audio gadget support at imx6 defconfig
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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fail log:
cpu_regulator-mx6.c: In function 'mx6_cpu_regulator_init':
cpu_regulator-mx6.c:87: error: 'loops_per_jiffy' undeclared
Signed-off-by: Tony Lin <tony.lin@freescale.com>
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NFS can work with WAIT mode only if the NFS use
TCPIP protoco, in order to test more features of
WAIT mode, we enable it by default and make sure
NFS is using TCPIP protocol.
Signed-off-by: Anson Huang <b20788@freescale.com>
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WAIT mode and DVFS still have some defects, we need
to disable it by default until we make them works.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add gpio keys for sabrelite
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Conflicts:
arch/arm/mach-mx6/board-mx6q_arm2.c
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1.modify some pins for support pfuze100
2.add mx6q_sabreauto_pmic_pfuze100.c to support regulator of pfuze100
3.modify imx6_defconfig to enable pfuze driver and regulator driver
Signed-off-by: Robin Gong <B38343@freescale.com>
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* Update esai pad settings for imx6q-ard platform
* Add reset and interrupt gpio macro definitions
* Attach cs42888 to correct i2c channel and rename
regulator dev_name and codec_name in accordance of
i2c channel.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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* imx6q-sabreauto esai pad settings
* Add mux pad setting for esai
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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* Remove platform regulators information for sgtl5000 codec
sgtl5000 codec not populated in imx6q-sabreauto platform
* Remove register sgtl5000 regulator devices
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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WAIT mode is enabled by default with this commit.
Adding "enable_wait_mode=off" to the command line will
prevent the system from entering WAIT mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Enable the USB video config as module avoid conflict with CSI camera
Enable the USB audio config as defult built in driver
Signed-off-by: make shi <b15407@freescale.com>
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add thermal driver support for android on mx6q boards;
enable fake power key for some boards
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Per e-mail from design team, the count needs to be zeroed and
reconfigured on exit from low power mode
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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* Add egalax touch screen support for sabreauto platform
* Add egalax client to correct i2c channel
* Fix GPIO assigned to touch screen interrupt
* egalax driver depends of LED_CLASS for gpio interrupt handling
and HIDRAW for X11 event notification and added to mx6q_defconfig
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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This commit intends to implement the flowchart and details
documented in the HDMI Transmitter Controller User Guide
section entitled "Programming Model".
Some input is also from the Synopsys API code.
The HDMI specification requires HDMI to set itself to VGA DVI mode
before reading the EDID.
So follow this sequence when HDMI is hotplugged:
1. Hdmi connector is plugged in, HDMI video gets an interrupt.
2. Clear out video mode list. Add only VGA DVI mode to list.
3. Request VGA DVI mode (call fb_set_var())
4. HDMI video driver will get FB_EVENT_MODE_CHANGE callback and
call mxc_hdmi_setup() to set up HDMI.
5. Read the edid and add video modes from edid. Select the video
mode that is similar to the command line default.
6. Request VGA DVI mode (call fb_set_var())
7. HDMI video driver will get FB_EVENT_MODE_CHANGE callback and
do mxc_hdmi_setup().
Also included is a workaround for an overflow condition in the HDMI.
The frame composer has an arithmetic unit that gets updated every time
we write to one of the FC registers. But sometimes, depending on the
relation between the tmds and sfr clocks, it may happen that this unit
doesn't get updated, even though the registers are holding correct
values. The workaround for this is, after completing the controller
configuration, to rewrite one of the FC registers (i.e. FC_INVIDCONF)
three or four times with the same value, and then follow it up by a SW
reset to the TMDS clock domain (MC_SWRSTZ).
We clear the overflow condition as described above every time we
change video mode. Also an overflow interupt handler will clear the
overflow condition if it happens again. This overflow condition is
expected (and not a problem) when we are in DVI (non-HDMI) mode, so
we do not worry about it in that case.
Signed-off-by: Alan Tull <alan.tull@freescale.com>
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* imx6sareauto fix i2c iomux pad settings
* On sabreaauto the i2c pad settings are missing in iomux-mx6q.h
* update i2c pad seetings and SD2 control pads
* Set correct i2c address for io expanders (expander A and B)
* explicit assert io expander reset line for normal operation mode
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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On mx6qsabrelite there is a total of 1GB of RAM.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Fixes problem sending "store added" events when there are multiple stores
Signed-off-by: Mike Lockwood <lockwood@android.com>
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Only CPU0 executes WFI followed by ISBs in uncached iRAM.
All other cores execute the regular cpu_do_idle()
This puts a restriction that all interrupts should only be routed to CPU0.
This bug should be fixed in TO1.1.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Read the silicon version stored in ROM at address ox48.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix incorrect frequencies reported from /proc/cpuinfo.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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* Update spdif config options for sabreauto platform
* Correct pad settings
* Only SPDIF RX in sabreauto, unset SPDIF TX support.
* spdif and i2c3 doesn't conflict in sabreauto platform
remove spdif early param and logic that set either pads.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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request cable detect pin when real init
Signed-off-by: Jason Chen <b02280@freescale.com>
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The chip document says the counter counts up to period_cycles + 1
and then is reset to 0, so the actual period of the PWM wave is
period_cycles + 2
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
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In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
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In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
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In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
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In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
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In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
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The change impact the mx5 bbg and loco build.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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PDK enabled dvfs core by default on kernel boot.
Android does not need such feature right now, so disable.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Need to push and pop all registers, otherwise, some registers
will be modified in the function call, add protection to avoid
this scenario.
Signed-off-by: Anson Huang <b20788@freescale.com>
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