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2014-04-25video: tegra: blank dc windows during dc releasedaily-2014.05.06.0_rel-roth-r4-partnerMichael Frydrych
Window owned by a process should be blanked when the process releases dc or any individual window it has owned. The buffers lastly displayed on those windows will be unpinned. bug 1490686 bug 1467689 Change-Id: I3b3614a99b9598b7d432f08c4a95d8050a4ef99e Signed-off-by: Michael Frydrych <mfrydrych@nvidia.com> Reviewed-on: http://git-master/r/400894 GVS: Gerrit_Virtual_Submit Reviewed-by: David Dastous St Hilaire <ddastoussthi@nvidia.com> Tested-by: David Dastous St Hilaire <ddastoussthi@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2014-04-22arch: arm: roth: Set backlight phase in rate to 32Ankita Garg
Some panels still show a change in brightness when booting even with smooth_k_incr value of 64. This change lowers the value to 32 and tested on 3 shield devices. Bug 1486835 Change-Id: Ica504769d0d4725270795aa329c94023590df34a Signed-off-by: Ankita Garg <ankitag@nvidia.com> Reviewed-on: http://git-master/r/390350 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ankit Pashiney <apashiney@nvidia.com>
2014-03-27arch: arm: roth: Reduce backlight phase in rateAnkita Garg
Bug 1486835 Change-Id: I2a42f272ff40d317083d8c9a1f6749ca91b9cbe4 Signed-off-by: Ankita Garg <ankitag@nvidia.com> Reviewed-on: http://git-master/r/388017 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Michael I Gold <gold@nvidia.com>
2014-03-15ARM: tegra: boot with performance freq governorSang-Hun Lee
- Set the CPU frequency governor to performance, once DVFS and clock initialization is done - Leave the initial CPU frequency governor to userspace, as initially CL-DVFS is not ready, thus the system is already at the highest frequency Bug 1458081 Change-Id: I29f3a023513e87d3c7411bda6daaf4000517fc72 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/382295 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
2014-03-06ARM: 7809/1: perf: fix event validation for software group leadersWill Deacon
commit c95eb3184ea1a3a2551df57190c81da695e2144b upstream. It is possible to construct an event group with a software event as a group leader and then subsequently add a hardware event to the group. This results in the event group being validated by adding all members of the group to a fake PMU and attempting to allocate each event on their respective PMU. Unfortunately, for software events wthout a corresponding arm_pmu, this results in a kernel crash attempting to dereference the ->get_event_idx function pointer. This patch fixes the problem by checking explicitly for software events and ignoring those in event validation (since they can always be scheduled). We will probably want to revisit this for 3.12, since the validation checks don't appear to work correctly when dealing with multiple hardware PMUs anyway. Reported-by: Vince Weaver <vincent.weaver@maine.edu> Tested-by: Vince Weaver <vincent.weaver@maine.edu> Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 40c366017f537354c64ea8b77d57ca81ecbd6b1d) Bug 1454622 Change-Id: I2b490a6955480c48586679de66bfba6c213b0247 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/367602
2014-03-06ARM: 7527/1: uaccess: explicitly check __user pointer when !CPU_USE_DOMAINSRussell King
commit 8404663f81d212918ff85f493649a7991209fa04 upstream. The {get,put}_user macros don't perform range checking on the provided __user address when !CPU_HAS_DOMAINS. This patch reworks the out-of-line assembly accessors to check the user address against a specified limit, returning -EFAULT if is is out of range. [will: changed get_user register allocation to match put_user] [rmk: fixed building on older ARM architectures] Reported-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 8cc876def310b034ab0e0775a14d1a49472d7f5f) Bug 1454622 Change-Id: I5802bb9426c06920e9849af560d7ea3862b6c852 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/367577
2014-01-24arm: configs: tegra11: enable hidrawToby Butzon
Bug 1425532. Reviewed-on: http://git-master/r/352340 Signed-off-by: Toby Butzon <tbutzon@nvidia.com> Change-Id: Ib656051a221a9879c4df8a766b458065d81f9b07 Reviewed-on: http://git-master/r/359122 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jean Huang <jeanh@nvidia.com> Reviewed-on: http://git-master/r/359505 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-01-24enable CONFIG_WIFI_CONTROL_FUNC to power up wifi chipNarayan Reddy
Bug 1422733 Change-Id: I0cc229259c3cc8652a47fd794c11019829290c50 Signed-off-by: Narayan Reddy <narayanr@nvidia.com> Reviewed-on: http://git-master/r/349386 Reviewed-by: Jean Huang <jeanh@nvidia.com> Tested-by: Jean Huang <jeanh@nvidia.com>
2013-12-17ARM: tegra: add otg driver entry for usb_vbus and vbus_bat_chgRakesh Bodla
Add the otg driver under device list for usb_vbus and vbus_bat_chg regulators. If USB port has OTG support, allow the OTG driver to control the vbus. Bug 1375608 Change-Id: I86253d145a6ff966e7a4e50deee695efe8545b88 Signed-off-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-on: http://git-master/r/334358 GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-12-16tegra: dc: enable CMU for secondary display.Markus Hiienkari
Enable CMU for secondary display as default. If DC type is HDMI, use sRGB-to-sRGB (limited range) conversion configuration. Bug 1162082 Bug 1162069 Bug 1407045 Change-Id: Ibb75ae0522fcf3aca6cffd3cfd747dfe5c6038bd Signed-off-by: Markus Hiienkari <mhiienkari@nvidia.com> Reviewed-on: http://git-master/r/337981 Reviewed-by: Thomas J. Meier <tmeier@nvidia.com> Reviewed-by: Xuezhou Ma <xuezhoum@nvidia.com> Reviewed-by: David Dastous St Hilaire <ddastoussthi@nvidia.com> Tested-by: David Dastous St Hilaire <ddastoussthi@nvidia.com> Reviewed-by: Michael I Gold <gold@nvidia.com>
2013-12-11ARM: tegra11x: wakeup: Fix sdmmc3 wakeup sourcePradeep Goudagunta
-Use gpio_pv2 as wakeup source for sdmmc3 card detect and disable sdmmc3 controller CD wakeup source. -Enabling both will conflict and results in failure of detection of SD card in device suspend state. Bug 1407948 Change-Id: Icdb98854ab1dc293924a33ed33e170a230979de6 Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-on: http://git-master/r/343668 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-11-06arm: tegra: Enable the ozwpan (USB HCD) driver.Todd Poynter
Enable the ozwpan USB HCD driver via CONFIG_USB_WPAN_HCD. Bug 1394137. Change-Id: If217707ea2f2cd215c93e7e42625abe4dc4eed4c Signed-off-by: Todd Poynter <tpoynter@nvidia.com> Reviewed-on: http://git-master/r/310142 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Toby Butzon <tbutzon@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2013-10-24arm: tegra: roth: Add pwm gpioAnshul Jain
Add pwm gpio in fan data, so it can be accessed by pwm_fan driver. Bug 1388303 Change-Id: I407166aac44473ec8ceaf4f8acee18b02db18d7f Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/302443 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2013-10-10ARM: tegra: disable IKCONFIG and make modules built-inEric Miao
Bug 1343930 To be conform with CTS, we need to disable IKCONFIG and MODULES, and make existing modules all built-in. CONFIG_MODULES and relevant options are left untouched, these will be turned OFF if it's a user build. This option is still necessary for engineering build for out-of-tree modules and many test cases. Change-Id: Icd858d5d707e66d4d9499de8ad358d06bc4e35d2 Signed-off-by: Eric Miao <eric.miao@nvidia.com> Reviewed-on: http://git-master/r/281984 Reviewed-by: Eric Miao <emiao@nvidia.com> Tested-by: Eric Miao <emiao@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-10-07mach-tegra: Enable LP0 wakeup on HDMI hotplug for board-roth.Todd Poynter
Set TEGRA_DC_OUT_HOTPLUG_WAKE_LP0 for roth_disp2_out which will arm the GPIO wakesource when set. Enable index WAKE4 / TEGRA_GPIO_PN7 (HDMI) as a wake source for board-roth. Bug 1367505. Change-Id: I4b4e3ca458243b3b27b316ac237264a0d323ff17 Signed-off-by: Todd Poynter <tpoynter@nvidia.com> Reviewed-on: http://git-master/r/281824 Reviewed-by: Dan Nolan <dnolan@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-10-04tegra: dc: hdmi: allow LP0 wakeup by hotplug GPIOAlexandre Courbot
Introduce a new TEGRA_DC_OUT_HOTPLUG_WAKE_LP0 flag which can be specified for DC controllers for which we want the HDMI hotplug GPIO to serve as a LP0 wake source. Bug 1345127 Change-Id: I9193be6ada4b0eca1c074c4b9a5888e3b0e49150 Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-on: http://git-master/r/266365 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aaron Gamble <jgamble@nvidia.com> Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/281798 Reviewed-by: Todd Poynter <tpoynter@nvidia.com> Tested-by: Todd Poynter <tpoynter@nvidia.com> Reviewed-by: Kevin Bruckert <kbruckert@nvidia.com>
2013-10-04ARM: tegra: add wakeup sources tuning functionsAlexandre Courbot
Add tegra_set_wake_gpio() and tegra_set_wake_irq() functions that allow board files to customize wakeup sources. Wake sources are fixed and currently defined in wakeups-t11x.c. Defining custom wake sources for a given project is difficult and can only be done by: 1) Having compilation conditionals into wakeups-t11x.c to perform per-board modifications (as is done for Dalmore currently), or 2) Duplicating wakeups-t11x.c and all the code it contains and compiling the corresponding wakeups sources file for the board. Neither or these methods can scale, and both actually break the ability to boot the same kernel binary on different boards. This patch exports functions that the board init functions can use to modify the wakeup sources as they need, keeping board-specific changes into board-specific files. Change-Id: I2803e5a76f2fc7eaaa9bd343c904719b018357bd Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-on: http://git-master/r/267689 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/281795 Reviewed-by: Todd Poynter <tpoynter@nvidia.com> Tested-by: Todd Poynter <tpoynter@nvidia.com> Reviewed-by: Kevin Bruckert <kbruckert@nvidia.com>
2013-09-16mmc: tegra: 1.39V Tuning during device enumerationPavan Kunapuli
Tuning at 1.39V to find a valid tap value that works at all core voltages. Boosting emc clock to 900MHz before setting 1.39V and releasing the frequency after 1.39V setting is removed. Bug 1331018 Reviewed-on: http://git-master/r/252471 (cherry picked from commit 25efc183d9f57431c379fecce0e2cc541b0fbc93) Change-Id: Icbf009a90ba9d0bd88a5991aab2fad8f1783b823 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Change-Id: I512a29e94cb935c12a8e705da1d4478c640c9529 Reviewed-on: http://git-master/r/274994 GVS: Gerrit_Virtual_Submit Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-09-16ARM: tegra: roth: Mask HS200 mode supportPavan Kunapuli
Mask HS200 mode support for sdmmc4. In DDR50 mode for eMMC can support max clock of 52MHz. For Tegra sdmmc controllers, the host clock in ddr mode should be double that of the eMMC device. Taking into consideration the dvfs tables, limiting ddr mode clock to 51MHz to allow for lower core voltages to set even when sdmmc4 clock is ON. Bug 1287739 BUg 1324297 Reviewed-on: http://git-master/r/230048 (cherry picked from commit d7214ec63a22383be14ee4f1fb424ad8e0f00364) Change-Id: Ib04dce91d771ab5505dd67ea3a8d5c704d0b499e Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Change-Id: I539439a3ccff3f75a25ea13198aa6267a7293dca Reviewed-on: http://git-master/r/274993 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-09-12ARM: tegra11: dvfs: Update T40T frequency limitsAlex Frid
Change-Id: I25851ce78f034ac592a0bd39ded1444f0a7e230d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/251056 (cherry picked from commit 5fae13057d44640c55a2fe5e09e118b6bacebd92) Reviewed-on: http://git-master/r/253674 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra: roth: Limit SD card clock to 82MHzPavan Kunapuli
Limiting SD card clock to 82MHz to ensure that the tap values obtained through tuning work with the full core voltage range even with boost mode enabled Reviewed-on: http://git-master/r/252371 (cherry picked from commit 0d07482e116768eb1dc413c940f4168e609a11fe) Change-Id: I562bb651d8eca8d412ea464cfbdca1b692783e55 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/253716 Reviewed-by: Harshada Kale <hkale@nvidia.com> Tested-by: Harshada Kale <hkale@nvidia.com>
2013-09-12ARM: tegra11: clock: Add emc and host1x sysfs floorsAlex Frid
Change-Id: Ia8bf319da85914e748c4a88877433e6c45667ef1 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250565 (cherry picked from commit 025b4feb4254f31a748ff926b225ffbde7960f1c) Reviewed-on: http://git-master/r/253682 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra: clock: Add sysfs interface for bus floorsAlex Frid
Added mechanism to install sysfs objects for tegra shared bus floors. Currently no floor objects are installed. Change-Id: I20e1a1448ee799a5ec59087f3214b77a80c05408 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250564 (cherry picked from commit caf42e72c877189dfc3b75d3d9d21fb2d2491fef) Reviewed-on: http://git-master/r/253681 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra11: clock: Expand host1x shared busAlex Frid
Add cap, floor, and override shared users to host1x bus. Attached cap user to core cap interface. Change-Id: I20bf5f346f422d7f2cbd97a445f00847e8761ac8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250563 (cherry picked from commit 01be9d99e4593df6fc149497d14bc4903e2bdd7e) Reviewed-on: http://git-master/r/253680 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra11: clock: Re-factor host1x busAlex Frid
- Set host1x dev_id = "host1x" and con_id = NULL (these definitions were used before conversion of host1x to shared bus; during conversion ids were inadvertently swapped - restored now) - Renamed host1x bus shared users to be consistent with other shared buses Change-Id: Iecf1f27681658c69fc63ed71c99d62ae86d9f30b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250562 (cherry picked from commit a96193452c05aca8596659a3a2f4346ad1818306) Reviewed-on: http://git-master/r/253679 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra11: clock: Add host1x shared busAlex Frid
Change-Id: Ie63f856727f9ba9f93e6c75b7bd5fb80357448a4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250561 (cherry picked from commit 2899d88dd8afa1971f2c1b09b7039852a65a5f4f) Reviewed-on: http://git-master/r/253678 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra: clock: Update emc monitor preset mechanismAlex Frid
- Allowed per-SoC code to select emc monitor preset rate. For now, rounded down boot rate is used as monitor preset rate (round down to not over-clock on boot). - Skipped emc clock update when monitor preset rate is set, but not yet enabled (to avoid temporary dip in EMC rate). EMC rate is updated only when monitor preset is enabled. - Preset EMC monitor rate after iso usage table is initialized. Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: I2b724df9dc95231d6a5760171aa18bd10bdb409a Reviewed-on: http://git-master/r/250525 (cherry picked from commit 0a3c757d15fc8360ba54e123907dbb4dd46c8d22) Reviewed-on: http://git-master/r/253677 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra11: clock: Preset EMC monitor rateAlex Frid
Use EMC boot rate as EMC monitor output reading during initialization until actual monitoring starts. Bug 1239168 Change-Id: I64d397623eeafe459769db106d0bfe80223f654f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250524 (cherry picked from commit 157a08636241aeb0886807190ab7d83b7e226c7b) Reviewed-on: http://git-master/r/253676 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra: clock: Record boot rates for all clocksAlex Frid
Change-Id: Iea43edd693d1489aa87eff893a1cfcfca1379552 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250523 (cherry picked from commit 42ce0d9e5770de7452f487493d033fece17bce88) Reviewed-on: http://git-master/r/253675 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra11: clock: Add cbus fine granularity regionAlex Frid
Added fine granularity region to cbus possible rates. In this region requested cbus rate is not clipped to dvfs steps, but rounded to fine granularity resolution. The latter is set as 12MHz, and the region is defined as 5 resolution steps below the top dvfs rate, assuming this top rate is reachable on the particular chip bin/sku. Change-Id: If1096ae068367819e64c55172c1a1c0a46c38b86 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250033 (cherry picked from commit 0c7b83bffdf79615bf15301f8643ac1dfabdefd9) Reviewed-on: http://git-master/r/253673 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra11: dvfs: Update T40T tables and limitsAlex Frid
Updated dvfs and edp tables, clock and voltage limits for T40T part. Change-Id: Ic256a6f3aa8026c96443ecc33204309275fcbe2e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250032 (cherry picked from commit d4add7fa3c1f5d26cb3a39e3431ca7c3fdb849e4) Reviewed-on: http://git-master/r/253672 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra11: power: Add T40T core edp tablesAlex Frid
Change-Id: Id5c2163224cdb1c862ef708e0790d99e4f04775e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250031 (cherry picked from commit 8c0649dc948f198068cce0086210309761194f82) Reviewed-on: http://git-master/r/253671 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra11: dvfs: Don't throttle T40T nominal voltageAlex Frid
On T40T parts removed throttling of nominal voltage by boot core edp. Used the latter to specify detached mode (boot, disable, suspend) limits. Change-Id: Ifa846ec8c7cb79df91b80cc81ffdef0f02a45372 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250030 (cherry picked from commit 08f29bd004f440272fdf75bf198638e9aceb8424) Reviewed-on: http://git-master/r/253670 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-12ARM: tegra: dvfs: Decouple nominal and detached voltagesAlex Frid
DVFS rail nominal voltage is minimum voltage required to run all associated clocks at maximum allowed rates. DVFS rail can be detached from clocks during initial boot, on suspend entry/exit, or when voltage scaling is disabled. So far, rail voltage in any detached mode was set to nominal level. This commit introduced separate voltages for each detached mode. If any of these levels is not specified, backward compatible nominal voltage is used. Since, suspend voltage may now be different from nominal (below), it is important for dvfs to suspend after suspend edp rate caps are set, and resume before edp. Hence, priorities of dvfs suspend notifiers were adjusted accordingly. Change-Id: Id05e0b16f24dc7d28b1ee9e87afd63d98a9ab86e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250029 (cherry picked from commit 57d1ea085f098f43db40a9484e5f9d13ec49a45b) Reviewed-on: http://git-master/r/253648 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-08-21tegra11: config: enable selinux to permissive modeJames Zhao
- Enable SELinux for JB MR2 - Set config option AUDIT, EXT4_FS_SECURITY for SELinux dependency Change-Id: I03a218ca421cc3337a82aca99e6c784732e6e650 Signed-off-by: James Zhao <jamesz@nvidia.com> Reviewed-on: http://git-master/r/257184 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-07-26ARM: tegra11: dvfs: Update CPU dvfs tablesAlex Frid
Bug 1291764 Change-Id: I92c652e9ecbec366c017ab2eda0e51b1dd42cb17 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/230033 (cherry picked from commit 8c42909312f5082d3e62f0fbc7b0556e7aed099d) Reviewed-on: http://git-master/r/242587 GVS: Gerrit_Virtual_Submit Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com> Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com>
2013-07-26ARM: tegra11: dvfs: Update DVFSMatt Wagner
Set CPU Vmin in DFLL mode 1.0V Change the tune high voltage to 1050mV Bug 1291764 Change-Id: I84a6854b0d7c85e602a6bc21d3fcb497613e5cae Signed-off-by: Matt Wagner <mwagner@nvidia.com> Reviewed-on: http://git-master/r/242586 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Sang-Hun Lee <sanlee@nvidia.com>
2013-07-26ARM: tegra: config: set panic timeout 5 secsJean Huang
Change-Id: I342d1f1505caedabaefa0b2f0eb5dccdf5046bca Signed-off-by: Jean Huang <jeanh@nvidia.com> (cherry picked from commit 7b01f4f1251efc02b2688c60fec162462f9c3aae) Reviewed-on: http://git-master/r/246201 Reviewed-by: Harshada Kale <hkale@nvidia.com> Tested-by: Harshada Kale <hkale@nvidia.com>
2013-07-12ARM: tegra: usb: Increase CPU frequency rangeRakesh Bodla
Now tegra chips cpu frequency has increased and updating the range accordingly. Bug 1216779 Change-Id: I57d530bcc5f4b8d5969ed7b5ffc21987e23809e8 Signed-off-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-on: http://git-master/r/207587 (cherry picked from commit e338bb00cb8e4b286147add38e652221b91ff73c) Reviewed-on: http://git-master/r/247769 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-07-10ARM: defconfigs: Enable Tegra profilerIgor Nabirushkin
Enable Tegra profiler for Tegra platforms Bug 1312406 Change-Id: If1bf645d40fec2de7ffcd17ac260deb0f8c2a4ee Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com> Reviewed-on: http://git-master/r/242401 Reviewed-by: Andrey Trachenko <atrachenko@nvidia.com> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Andrey Trachenko <atrachenko@nvidia.com>
2013-07-10ARM: kprobes: Fix kprobes buildIgor Nabirushkin
Fix incorrect changes in the arch_arm_kprobe function (commit: 3b3f4d24917c97fa75aa4fba2b09797ef94cea38) Bug 1228659 Change-Id: Iee16e3d5f6475acd9cd08060b16d015e8757a286 Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com> Reviewed-on: http://git-master/r/208435 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Andrey Trachenko <atrachenko@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Tested-by: Andrey Trachenko <atrachenko@nvidia.com>
2013-07-09arm: tegra: roth: Enable FAST init mode for smps9Anshul Jain
Bug 1315200 Change-Id: If1bfc2a17d302f10b4d5439fa5e1ba5914b2fcc5 Signed-off-by: Anshul Jain <anshulj@nvidia.com> (cherry picked from commit a85da1ba4c7249722caf3c0c75683f08cc0860e1) Reviewed-on: http://git-master/r/246316
2013-07-09misc: issp: Add usb js recovery mechanismAnshul Jain
This change recovery the JS uC after USB resume failure by unloading USB, resetting uC from ISSP and then reloading USB Bug 1306389 Change-Id: I086636d4b7b91e3a2874f584fa6efbfd2cae6014 Signed-off-by: Michael Hsu <mhsu@nvidia.com> Signed-off-by: Anshul Jain <anshulj@nvidia.com> (cherry picked from commit e10f9579dbd6e3d37b127995520b9dee036be199) Reviewed-on: http://git-master/r/246314
2013-06-18arm: tegra: board support for sensorsErik Lilliebjerg
Added support for BMP180 pressure sensor and auto-detection of AKM89XX compass. Change-Id: I3e45250e7b4e2887d79bd62a402ddcdc0d057b92 Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com> Reviewed-on: http://git-master/r/211081 (cherry picked from commit 00811e96be2c6ac4139a6b24b39cf44ddcf20bda) Reviewed-on: http://git-master/r/216710 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Xiaohui Tao <xtao@nvidia.com> Tested-by: Xiaohui Tao <xtao@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2013-06-18arm: tegra: configs: Add BMP180 moduleErik Lilliebjerg
Add BMP180 pressure sensor driver as module. Bug 1253718 Bug 1242566 Change-Id: Ia2de59ccbe833b9f444fb56234954729edf7b5a3 Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com> Reviewed-on: http://git-master/r/210854 (cherry picked from commit f891baec733e839d02c220fcb934097c29a266be) Reviewed-on: http://git-master/r/216711 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Xiaohui Tao <xtao@nvidia.com> Tested-by: Xiaohui Tao <xtao@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2013-06-11ARM: tegra: dvfs: Don't fail same level override requestAlex Frid
When new VDD_CORE override level is the same as the one already in place do not return error from the override API. Bug 1280293 Change-Id: Ic4393541308139c2ac9579acc8e2af47b144d521 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/225037 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Matt Wagner <mwagner@nvidia.com>
2013-06-05ARM: Tegra: Roth: Increase Drive Strength for 4KMatt Wagner
Increase by 30mV Bug 1278943 Change-Id: I554c281ca1f12cb7494516844f4fd72e1d4b03b1 Signed-off-by: Matt Wagner <mwagner@nvidia.com> (cherry picked from commit e61f283f9966358e68c7cdcd9ea26bbc7bbc18c3) Reviewed-on: http://git-master/r/230045 Reviewed-on: http://git-master/r/232704 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2013-06-04ARM: SMP: disable preempt before SMP cross callBo Yan
preemption should be disabled when smp_call_function_many is called. bug 1224910 Change-Id: I4c23e6fe77354d50230b8e46bcc4128a9888f201 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/222644 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> (cherry picked from commit 252748d9f3e90b7ab36a50b8b10912c183ca67f4) Reviewed-on: http://git-master/r/233913 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Sang-Hun Lee <sanlee@nvidia.com>
2013-06-04ARM: tegra11x: Enable ARM_ERRATA_798181Bo Yan
Change-Id: I533f1965a93694484a910723c77454a0bd9e5fe0 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/209853 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com> (cherry picked from commit 1927a8824de27eea314d7b1a4ac08741edb6daba) Reviewed-on: http://git-master/r/221354 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Sang-Hun Lee <sanlee@nvidia.com>
2013-06-04arm: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)Catalin Marinas
On Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down all use of the old entries. This patch implements the erratum workaround which consists of: 1. Dummy TLBIMVAIS and DSB on the CPU doing the TLBI operation. 2. Send IPI to the CPUs that are running the same mm (and ASID) as the one being invalidated (or all the online CPUs for global pages). 3. CPU receiving the IPI executes a DMB and CLREX (part of the exception return code already). The switch_mm() code includes a DMB operation since the IPI is only sent to CPUs running the same ASID. Change-Id: Ideb7f479910f7d4bf25182c84eb5e71691c42a93 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/209830 (cherry picked from commit e11ccb30b44fc55ba0576f5082e5e17e9a1d1854) Reviewed-on: http://git-master/r/221353 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Sang-Hun Lee <sanlee@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-02 23:28:17 +0000