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On imx6sx, bit 17 and bit18 will power off/on VADC directly,
so read GPC_CNTR firstly before write to avoid touching other bits.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit ce70fc330c33dd33a73e2f1c8d00f29ec4d68b1d)
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For the QSPI byte address not aligned in ROM code and kernel, we have to reset
power cycle to workaroud this issue. Use WDOG_B pin to trigger PWRON of pfuze.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 86f82eadc612a746ab57760f78754e0619aa48b1)
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SSI and SSI_IPG are controlled by the same clock gating bits, so register
them with imx_clk_gate2_shared.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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SSI and SSI_IPG are controlled by the same clock gating bits, so register
them with imx_clk_gate2_shared.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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SAI and SAI_IPG are controlled by the same clock gating bits, so register
them with imx_clk_gate2_shared.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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When the busfreq is in audio_bus_freq_mode, the AHB bus is at 8MHz,
in low_bus_freq_mode, the AHB needs to run at 24MHz. So when switching
from audio_bus_freq_mode to low_bus_freq_mode, make sure the AHB is at
24MHz in low_bus_freq_mode.
Signed-off-by: Bai Ping <b51503@freescale.com>
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The CAN transceiver on MX6SX Sabreauto board seems in sleep mode
by default after power up the board. User has to press the wakeup
key on ARD baseboard before using the transceiver, or it may not
work properly when power up the board at the first time(warm reset
does not have such issue).
This patch wakeup the transceiver firstly if needed during intialization
by control the wakeup pin, then user do not have to press wakeup key
button to enable the transceiver.
BTW, stby gpio is also updated which is wrong before.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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NAND scans the bad blocks during kernel boots up, which invokes the
gpmi_ecc_read_oob function to check the badblock mark for each block. In
this function the oob data was raw read from NAND chip without ECC, so
it hardly to guarantee the consistency of the data considering the
possible bitflips. It found that in some MLC NAND the oob data changed
and consequently the BBT changed in different power cycles. This issue
may cause the UBIFS mount failed.
To fix this issue, add "nand_on_flash_bbt" option in dts to store the BBT
in NAND flash. On the first time kernel boot up, all bad blocks and
probably some fake bad block would be recognized and be recorded in
on-nand bad block table. From the second time boot, kernel will read BBT
from NAND Flash rather than calling gpmi_ecc_read_oob function to check
bad block.
No bad block would be missed when create BBT since the probability that
16bit bad block mark filps from 0x00 to 0xFF is extremely low.
Signed-off-by: Allen Xu <b45815@freescale.com>
(cherry picked from commit d957353768a1b6d39b340b9d10b22fc42b0aa8e2)
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use the string "okay" instead to enable backlight
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit 5468fd8a98086ec68347f92c4a525ea4c1b71c5f)
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Update the i.MX6DL cpu operating points to comply with the latest
published datasheet. Latest i.MX6DL datasheet of Rev.4, 10/2014
updates the 396MHz setpoint's min voltage from 1.075V to 1.125V, Add a
25mV margin to cover the board IR drop, here use 1.15V for 396MHz to
match datasheet.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Add the ddrsmp parameter for 19x19 arm2 board.
2 ---- i.MX6SX 19x19 ARM2 board
And reduce the clock frequency from 53Mhz to 29Mhz.
Signed-off-by: Allen Xu <b45815@freescale.com>
(cherry picked from commit 44a1d6c7b438fa1139572e864ee6aa111de39f18)
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The ddr sample point is board related, so add ddrsmp parameter to device
tree for i.MX6SX 17x17 ARM2 board.
DDRSMP value:
2 ---- i.MX6SX 17x17 ARM2 board
Signed-off-by: Allen Xu <b45815@freescale.com>
(cherry picked from commit c5d9eb443cda0c4d6e5705a2b51904f49b4f8297)
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Since QSPI internal DDR sample point is relevant with board layout,
we can't use same value for all boards. Add ddrsmp parameter to device
tree for i.MX6SX Sabreauto/Sabresd board.
DDRSMP value:
0 ---- i.MX6SX Sabresd board (RevB and RevA)
2 ---- i.MX6SX Sabreauto board
The Sabresd RevA board also needs to reduce clock to 29Mhz according to
the Spansion spec.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit c9115cc22d836b5b980ca20932a005ea61b20082)
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imx_clk_gate2_flags() uses CGR value 2b'11, while imx_clk_gate()
use CGR value 2b'01. We need 2b'11 which means "clock is on during
all modes, except STOP mode".
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit 51841a54f6746ce06b16a3297014069a2b3b97c2)
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Previously PWM3 is always enabled even when the LCDIF1 is not used.
This is not correct, since the default DTS file enables CSI while
disable LCDIF1 due to pin conflict between CSI and LCDIF1 on imx6sx-sdb board.
This patch fixed it.
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit f77c15ccab9e8a68870048d4964b2dd15b3d4c0c)
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imx6sl
If system is in audio busfreq mode, when entering low power idle, set the MMDC podf
to 8 for power saving. Before exiting low power idle, the PODF value need to be restored
to the original value.
Signed-off-by: Bai Ping <b51503@freescale.com>
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M4 can NOT switch its clk parent due to glitch MUX,
to handle this case, A9 will help switch M4's clk
parent, the flow is as below:
M4:
1. enter low power idle, send bus use count-- to A9;
2. enter wfi and only wait for MU interrupt;
3. receive A9's clk switch ready message, go into low
power idle;
4. receive interrupt to exit low power idle, send request
to A9 for increase busfreq and M4 freq, enter wfi
and only wait for MU interrupt;
5. receive A9 ready message, go out of low power idle.
A9:
1. when receive M4's message of entering low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to OSC, ungate M4 clk,
send ready command to wake up M4 into low power idle;
2. when receive M4's message of exiting low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to origin high clk,
ungate M4 clk, send ready command to wake up M4
to exit low power idle;
Signed-off-by: Anson Huang <b20788@freescale.com>
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As M4's clk switch MUX is NOT a glitchless one, when M4 try to
switch its parent, it needs to be gated, so M4 can NOT switch its
parent by itself, need A9 to help do it.
Have to remove M4 from shared memory, it means M4's clk will be
managed by A9 completely.
Signed-off-by: Anson Huang <b20788@freescale.com>
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For DCIC module all lcdif data and signal pins
should configuration to SION(Software Input On Field)
to enable loopback mode.
But the pin of LCD1_RESET not required,
so remove SION setting otherwise imx6sx sdb board can not
resume from power suspend.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit ada39ddc49f527672281e510abe06d3f40559383)
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Reduced the QSPI clock from 53Mhz to 29Mhz according to spec requirement
Signed-off-by: Allen Xu <b45815@freescale.com>
(cherry picked from commit ea5d6d29564c29b21d117056e9cbd1430199b4de)
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add sdb revA board QSPI legacy support for Spansion QSPI chip.
Signed-off-by: Allen Xu <b45815@freescale.com>
(cherry picked from commit 3fd143ae78007e58d1dc45bc829b462a12b93cd2)
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Previously the pixel clock for LCDIF and EPDC shares the same parent clock
PLL5_VIDEO. This will bring the following error boot message:
clk_pllv3_av_set_rate: cannot configure divider when PLL is powered on
The reason is the dual-display case breaks the rule added by the
patch "93a9e3d0b88203cb523dd92e85590683d6a85fdf ENGR00318063-6:
ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocks" which adds the
requirement "the clock must be gated across rate change"
After LCDIF pixel clock is configured and enabled, EPDC pixel clock
need to be configured also but the parent PLL is already enabled by
LCDIF driver thus the configuration will fail.
On i.MX6SL, we need support LCD display and EPDC display simultaneously,
then we cannot disable the PLL clock when LCD or EPDC is working already.
So we switch the parent for EPDC pixel clock to PLL2_PFD1.
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit 8aa38347f486124f0bcec767b721a820fbae7010)
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imx6sx-sabreauto board
There are two places descript the i2c2 bus, remove one to make the
dts file pithily.
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
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set the dual bsd/gpl copyright of the mcc platform related codes
implemented in linux bsp release.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
(cherry picked from commit dba21205c981cb38e18ec2b58f42cb726b519bea)
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set the dual bsd/gpl copyright of the mcc common codes
implemented in linux bsp release.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
(cherry picked from commit d7f8c4eff50ba78b82484597bd301c4a87dfe082)
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Update the imx6Q cpu operating points to comply with the latest
published datasheet. Latest i.MX6Q datasheet of Rev.3, 02/2014
updates the 792MHz setpoint's min voltage from 1.125V to 1.15V, Add a
25mV margin to cover the board IR drop, here use 1.175V for 792MHz to
match datesheet.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Add uart5 support for imx6sx-sabreauto board.
(cherry-pick from commit: 85755102aeeefc0e1c7e6c5523ec636473e81a2c)
Signed-off-by: Fugang Duan <B38611@freescale.com>
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FEC1 port was disabled since the ethernet daughter board cannot
plugin to the ethernet EXP port in socket board that is blocked
by the socket. For solid board, it is not problem, so enable FEC1
port in default.
(cherry-picked from commit f0c7b2324a3c539846c001599280c262c6f6b71d)
Signed-off-by: Fugang Duan <B38611@freescale.com>
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When resume from DSM with Mega/Fast off, we need to restore
the right QSPI module for M4, so get the qspi index from dtb file.
Signed-off-by: Anson Huang <b20788@freescale.com>
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As on different boards, MQX may run on different QSPI
module, such as i.MX6SX SDB board using QSPI2, and i.MX6SX
SABREAUTO using QSPI1, so here we add a node to tell kernel
which QSPI module need to be restored after resume from
DSM mode with Mega/Fast off, by default it is for QSPI2 to
align with i.MX6SX SDB board, modify the baord dtb file to
change it.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add M4 support for i.MX6SX SABREAUTO board.
Signed-off-by: Anson Huang <b20788@freescale.com>
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added BT config to imx_v7_defconfig to enable the BT interface in Linux
kernel by default.
Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com>
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The CANFD IP will be removed in final production, so remove
the CANFD related stuff in dts tree to avoid confusion.
The patch only removed user level in dts part, the exists related
clocks and pads in source code are still there which seems not matter.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Detailed reproduce steps:
1. boot-up to Linux command prompt .
2. Plug SD3.0 UHS-I SD Card into SD3 Connector (make sure SD Card running
at SD3.0 DDR50/1.8V).
2. write data to SD3 using "dd" command (SD3_CLK running at 1.8V/50MHz).
3. capture the SD3_CLK, SD3_DATA, SD3_CMD waveforms during data write using
FET probe (>=1GHz)
4. CLK waveforms like triangular wave are observed.
HW team found that the pad setting of the SD3_CLK, SD3_DATA, SD3_CMD signal pins are
not optimized. In existing BSP, when running at SD3.0/DDR50/1.8V, SPEED/DSE/SRE
= 01/011/1 is used. They propose change it to -
SD3_CLK: SPEED/DSE/SRE = 01/110/1.
SD3_DATA/SD3_CMD: SPEED/DSE/SRE = 01/101/1.
SDHC high speed cards also had such issue(refer to MLK-9500).
We only changed the default state (<50Mhz) pad setting, for ultra high speed
state like 100Mhz and 200Mhz, it does not have such issue since they already
set to the maximum Drive Strength value.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Detailed reproduce steps:
1. boot-up to Linux command prompt.
2. send data from CAN device using "candump" command.
3. capture the TXD waveform during transmission.
4. severe overshoot/undershoot is observed (+4.4V ~ -1.2V).
HW team found that the pad setting of the CAN signal pins is not optimized.
In existing BSP, SPEED/DSE/SRE = 10/110/1 is used. They propose change it
to SPEED/DSE/SRE = 00/100/0.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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QSPI chip changed from spansion s25fl128s to micron n25q256a
Signed-off-by: Allen Xu <b45815@freescale.com>
(cherry picked from commit 56c87a201946e4582de2f574c218e43c4db7fadb)
(cherry picked from commit 628c08401cf3b6fcd477bdf118269b0c868e16d8)
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add flexcan devices support
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 5a4fd0864013a5e50b6cdb8132fc4caf15aa1d4b)
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CAN devices are allocated to run on M4.
So do not touch CAN pads setting if M4 is enabled.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Since CAN device is allocated to run on M4 and handled by M4 if M4 is enabled,
so we do not set CAN parent clock when M4 is enabled.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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If there is pending irq before entering DSM, the CCM will NOT enter
stop mode, so the resume code will go to the backup path, but we
miss the restore of RDC clks, it will cause the DDR/IO restore fail.
As only i.MX6SX has Mega/Fast mix off feature, eim_slow clk and
PCIe clk are only necessary for i.MX6SX's RDC resume, add CPU
type check to avoid any surprise for other i.MX6 platforms.
Signed-off-by: Anson Huang <b20788@freescale.com>
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There is scenario that A9 will keep handling M4's wakeup source
interrupt and lead to kernel dead loop, for example, CAN driver
is enabled in M4, but in order to make sure it can wake up A9
from wfi when linux failed to enter DSM mode, we have to enable
CAN's irq in GIC as well, but we do NOT clear CAN's module irq
when handling CAN's irq, it depends on M4 to clear CAN's hardware
irq. Here comes problem, when CAN irq wake up A9, A9 will schedule
a delay work to tell M4 it is ready to wakeup, only after M4 is
waked up, it can handle the CAN interrupt, so A9 will keep receiving
CAN irq and the delay work has no chance to run, so it cause linux
dead loop in interrupt context.
The solution is to keep M4's wakeup source always disabled in GIC,
only when linux is about to enter DSM mode, then these wakeup
sources will be enabled in GIC, that needs to set the IRQF_NO_SUSPEND
flag, then GIC mask/unmask will be accessed by calling common
enable_irq/disable_irq API.
Also, this patch adds the transfer status check before sending
a message to M4, this is to make sure A9 does NOT overwrite any
message.
Signed-off-by: Anson Huang <b20788@freescale.com>
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mcc_generate_cpu_to_cpu_interrupt maybe failed, set the func
type of the mcc_generate_cpu_to_cpu_interrupt to int.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
(cherry picked from commit 74b859788792fb59b8751468bd34cd2c6ee9025e)
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This change is similar to the commit a18916031e02442893d20ea0529041402cb16d48.
Currently the CSI clock is only derived from OSC 24Mhz instead of PLL.
Only use imx_clk_gate2_flags() without CLK_SET_RATE_GATE flag.
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit 6db3062095de4d9ff3ac49dcf1218906138497d8)
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need to call imx_clk_gate2 with specific flags for i.mx6sl CSI case.
we can not just use imx_clk_gate() because clock gating bits 2b'01
seems not work for CSI while 2b'11 works. However imx_clk_gate2()
has the fixed flags which does not fit CSI case.
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit 6ec90260a7431829cd5a7a05c9a0635f0236245e)
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By default, uboot set uart clk parent to OSC to make UART work when M4
is enabled. In the situation, uart maximum baud rate only reach at 1.5Mbps
that cannot match real case requirement.
The patch set the uart module clock source to pll3_80m in default. If
test low power case, it needs to add "uart_from_osc" in kernel command line.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit 2e4986437817a5e4ff251a0594abcf3614e52a20)
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Enable USB OTG2 as a host only port.
Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit 11c9528c60e0452ba9ce1a53f673be2fc3c04813)
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Enable several USB ethernet drivers, they are built as module.
Acked-by: Li Jun <b47624@freescale.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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As we have specific tag and data latency settings on our platforms,
so we have to restore these settings after resume with L2 controller
power gated. Otherwise, system perpormance will be impacted a lot:
dd read test(dd if=/dev/mmcblk2 of=/dev/null bs=1M count=2000) of SD
card would lower from 61.4MB/s to 57.7MB/s, ~6% drop.
Signed-off-by: Anson Huang <b20788@freescale.com>
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QSPI-NOR reboot failed in case of larger flash size such as 256M used, because
kernel QSPI-NOR flash use 4-bytes-address mode to visit 16MB+ area but ROM code
use 3-bytes-address mode to access QSPI-NOR. Thus, we have to use WDOG_B to
reset QSPI-NOR flash to workaround this.
Note:
Please update the u-boot with the below u-boot patch, otherwise system will
reboot endless while kernel boot:
"MLK-9819: ARM: mx6sx: clear WDOG3 Power Down Enable bit for i.mx6sx"
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 89b88be2a870124d58080970b37f93d868093e9a)
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add the CONFIG_CPU_FREQ_GOV_PERFORMANCE, enable the performance
governor on 3.10 branch
Signed-off-by: Bai Ping <b51503@freescale.com>
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