Age | Commit message (Expand) | Author |
2020-12-21 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds |
2020-11-26 | clk: meson: g12a: add MIPI DSI Host Pixel Clock | Neil Armstrong |
2020-11-23 | clk: meson: enable building as modules | Kevin Hilman |
2020-11-23 | clk: meson: Kconfig: fix dependency for G12A | Kevin Hilman |
2020-11-23 | clk: meson: axg: add MIPI DSI Host clock | Neil Armstrong |
2020-11-23 | clk: meson: axg: add Video Clocks | Neil Armstrong |
2020-11-14 | clk: meson: g12: use devm variant to register notifiers | Jerome Brunet |
2020-11-14 | clk: meson: g12: drop use of __clk_lookup() | Jerome Brunet |
2020-10-28 | clk: define to_clk_regmap() as inline function | Arnd Bergmann |
2020-10-20 | Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', ... | Stephen Boyd |
2020-10-13 | clk: meson: use semicolons rather than commas to separate statements | Julia Lawall |
2020-09-10 | clk: meson: make shipped controller configurable | Jerome Brunet |
2020-08-29 | clk: meson: g12a: mark fclk_div2 as critical | Stefan Agner |
2020-08-17 | clk: meson: axg-audio: fix g12a tdmout sclk inverter | Jerome Brunet |
2020-08-17 | clk: meson: axg-audio: separate axg and g12a regmap tables | Jerome Brunet |
2020-08-17 | clk: meson: add sclk-ws driver | Jerome Brunet |
2020-07-21 | Merge branch 'clk-amlogic' into clk-next | Stephen Boyd |
2020-07-10 | Replace HTTP links with HTTPS ones: Common CLK framework | Alexander A. Klimov |
2020-07-09 | clk: meson: meson8b: add the vclk2_en gate clock | Martin Blumenstingl |
2020-07-09 | clk: meson: meson8b: add the vclk_en gate clock | Martin Blumenstingl |
2020-06-24 | clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 | Martin Blumenstingl |
2020-06-19 | clk: meson: g12a: Add support for NNA CLK source clocks | Dmitry Shmidt |
2020-05-02 | clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers | Martin Blumenstingl |
2020-04-29 | clk: meson: meson8b: Make the CCF use the glitch-free VPU mux | Martin Blumenstingl |
2020-04-29 | clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits | Martin Blumenstingl |
2020-04-29 | clk: meson: meson8b: Fix the polarity of the RESET_N lines | Martin Blumenstingl |
2020-04-29 | clk: meson: meson8b: Fix the first parent of vid_pll_in_sel | Martin Blumenstingl |
2020-04-16 | clk: meson: g12a: Prepare the GPU clock tree to change at runtime | Martin Blumenstingl |
2020-04-16 | clk: meson: gxbb: Prepare the GPU clock tree to change at runtime | Martin Blumenstingl |
2020-04-14 | clk: meson: meson8b: make the hdmi_sys clock tree mutable | Martin Blumenstingl |
2020-04-14 | clk: meson8b: export the HDMI system clock | Martin Blumenstingl |
2020-02-21 | clk: meson: meson8b: set audio output clock hierarchy | Martin Blumenstingl |
2020-02-19 | clk: meson: g12a: add support for the SPICC SCLK Source clocks | Neil Armstrong |
2020-02-13 | clk: meson: gxbb: set audio output clock hierarchy | Jerome Brunet |
2020-02-13 | clk: meson: gxbb: add the gxl internal dac gate | Jerome Brunet |
2020-01-31 | Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlo... | Stephen Boyd |
2020-01-07 | clk: meson: meson8b: make the CCF use the glitch-free mali mux | Martin Blumenstingl |
2019-12-23 | clk: let init callback return an error code | Jerome Brunet |
2019-12-16 | Merge branch 'v5.5/fixes' into v5.6/drivers | Jerome Brunet |
2019-12-16 | clk: meson: pll: Fix by 0 division in __pll_params_to_rate() | Remi Pommarel |
2019-12-16 | clk: meson: g12a: fix missing uart2 in regmap table | Jerome Brunet |
2019-12-11 | clk: meson: meson8b: use of_clk_hw_register to register the clocks | Martin Blumenstingl |
2019-12-11 | clk: meson: meson8b: don't register the XTAL clock when provided via OF | Martin Blumenstingl |
2019-12-11 | clk: meson: meson8b: change references to the XTAL clock to use [fw_]name | Martin Blumenstingl |
2019-12-11 | clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier | Martin Blumenstingl |
2019-12-11 | clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller | Martin Blumenstingl |
2019-10-14 | clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code | YueHaibing |
2019-10-08 | clk: meson: axg_audio: add sm1 support | Jerome Brunet |
2019-10-08 | clk: meson: axg-audio: provide clk top signal name | Jerome Brunet |
2019-10-08 | clk: meson: axg-audio: prepare sm1 addition | Jerome Brunet |