linux-toradex.git - Linux kernel for Apalis and Colibri modules

Age	Commit message (Expand)	Author
2017-08-23	clk: tegra: Fix T210 PLLRE registration	Alex Frid
2017-08-23	clk: tegra: Update T210 PLLSS (D2/DP) registration	Alex Frid
2017-08-23	clk: tegra: Re-factor T210 PLLX registration	Alex Frid
2017-08-23	clk: tegra: change post IDDQ release delay to 5us	Peter De Schrijver
2017-08-23	clk: tegra: Init cfg structure in _get_pll_mnp	Peter De Schrijver
2017-08-23	clk: tegra: Enable PLL_SS for Tegra210	Peter De Schrijver
2017-08-23	clk: tegra: fix SS control on PLL enable/disable	Peter De Schrijver
2017-03-20	clk: tegra: Rework pll_u	Peter De Schrijver
2016-06-30	clk: tegra: Initialize UTMI PLL when enabling PLLU	Andrew Bresticker
2016-04-28	clk: tegra: Fix pllre Tegra210 and add pll_re_out1	Rhyland Klein
2016-02-02	clk: tegra: Fix PLLE SS coefficients	Mark Kuo
2016-02-02	clk: tegra: Fix typos around clearing PLLE bits during enable	Rhyland Klein
2016-02-02	clk: tegra: Do not disable PLLE when under hardware control	Mark Kuo
2016-02-02	clk: tegra: pll: Fix potential sleeping-while-atomic	Andrew Bresticker
2015-12-17	clk: tegra: Read correct IDDQ register in PLL_SS registration	Bill Huang
2015-12-17	clk: tegra: Fix WARN_ON in PLL_RE registration	Bill Huang
2015-12-17	clk: tegra: pll: Fix issues with rates for VCO PLLs	Andrew Bresticker
2015-12-17	clk: tegra: Add support for Tegra210 clocks	Rhyland Klein
2015-12-17	clk: tegra: pll: Add logic for SS	Bill Huang
2015-12-17	clk: tegra: pll: Add dyn_ramp callback	Rhyland Klein
2015-12-17	clk: tegra: pll: Add Set_default logic	Bill Huang
2015-12-17	clk: tegra: pll: Adjust vco_min if SDM present	Bill Huang
2015-12-17	clk: tegra: pll: Add support for PLLMB for Tegra210	Rhyland Klein
2015-12-17	clk: tegra: pll: Add specialized logic for Tegra210	Rhyland Klein
2015-11-20	clk: tegra: pll: Update PLLM handling	Danny Huang
2015-11-20	clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate	Rhyland Klein
2015-11-20	clk: tegra: pll: Add code to handle if resets are supported by PLL	Bill Huang
2015-11-20	clk: tegra: pll: Add logic for out-of-table rates for T210	Rhyland Klein
2015-11-20	clk: tegra: pll: Add logic for handling SDM data	Rhyland Klein
2015-11-20	clk: tegra: pll: Don't unconditionally set LOCK flags	Rhyland Klein
2015-11-20	clk: tegra: pll: Update warning message	Rhyland Klein
2015-11-20	clk: tegra: pll: Simplify clk_enable_path	Rhyland Klein
2015-11-20	clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header	Rhyland Klein
2015-11-20	clk: tegra: Constify pdiv-to-hw mappings	Thierry Reding
2015-11-18	clk: tegra: Miscellaneous coding style cleanups	Thierry Reding
2015-08-24	clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)	Stephen Boyd
2015-08-24	clk: tegra: Convert to clk_hw based provider APIs	Stephen Boyd
2015-07-20	clk: tegra: Properly include clk.h	Stephen Boyd
2015-04-10	clk: tegra: Remove needless initializations	Thierry Reding
2015-04-10	clk: tegra: Various whitespace cleanups	Thierry Reding
2015-02-02	clk: tegra: Add support for the Tegra132 CAR IP block	Paul Walmsley
2015-02-02	clk: tegra: Fix order of arguments in WARN	Tomeu Vizoso
2014-07-08	clk: tegra: Use XUSB-compatible SATA PLL sequence	Mikko Perttunen
2014-06-25	clk: tegra: Enable hardware control of SATA PLL	Mikko Perttunen
2014-05-28	Merge branch 'clk-fixes' into clk-next	Mike Turquette
2014-05-27	Merge tag 'clk-tegra-fixes-3.15' of git://nv-tegra.nvidia.com/user/pdeschrijv...	Mike Turquette
2014-05-22	clk: tegra: Enable hardware control of PLLE	Jim Lin
2014-05-16	clk: tegra: Fix wrong value written to PLLE_AUX	Tuomas Tynkkynen
2014-04-17	clk: tegra: Fix enabling of PLLE	Thierry Reding
2014-04-17	clk: tegra: Introduce divider mask and shift helpers	Thierry Reding