Age | Commit message (Expand) | Author |
2016-06-30 | clk: tegra: Initialize UTMI PLL when enabling PLLU | Andrew Bresticker |
2016-04-28 | clk: tegra: Fix pllre Tegra210 and add pll_re_out1 | Rhyland Klein |
2016-04-28 | clk: tegra: Add fixed factor peripheral clock type | Thierry Reding |
2016-04-28 | clk: tegra: Constify peripheral clock registers | Thierry Reding |
2015-12-17 | clk: tegra: Add support for Tegra210 clocks | Rhyland Klein |
2015-12-17 | clk: tegra: Add Super Gen5 Logic | Bill Huang |
2015-12-17 | clk: tegra: pll: Add logic for SS | Bill Huang |
2015-12-17 | clk: tegra: pll: Add dyn_ramp callback | Rhyland Klein |
2015-12-17 | clk: tegra: pll: Add Set_default logic | Bill Huang |
2015-12-17 | clk: tegra: pll: Adjust vco_min if SDM present | Bill Huang |
2015-12-17 | clk: tegra: pll: Add support for PLLMB for Tegra210 | Rhyland Klein |
2015-12-17 | clk: tegra: pll: Add specialized logic for Tegra210 | Rhyland Klein |
2015-11-20 | clk: tegra: pll: Add code to handle if resets are supported by PLL | Bill Huang |
2015-11-20 | clk: tegra: pll: Add logic for out-of-table rates for T210 | Rhyland Klein |
2015-11-20 | clk: tegra: pll: Add logic for handling SDM data | Rhyland Klein |
2015-11-20 | clk: tegra: pll: Change misc_reg count from 3 to 6 | Bill Huang |
2015-11-20 | clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header | Rhyland Klein |
2015-11-20 | clk: tegra: Constify pdiv-to-hw mappings | Thierry Reding |
2015-10-20 | clk: tegra: Modify tegra_audio_clk_init to accept more plls | Rhyland Klein |
2015-10-20 | clk: tegra: Update struct tegra_clk_pll_params kerneldoc | Thierry Reding |
2015-10-20 | clk: tegra: Fix comments for structure definitions | Rhyland Klein |
2015-07-16 | clk: tegra: Introduce ability for SoC-specific reset control callbacks | Mikko Perttunen |
2015-05-13 | clk: tegra: EMC clock driver depends on EMC driver | Thierry Reding |
2015-05-13 | clk: tegra: Add EMC clock driver | Mikko Perttunen |
2015-04-10 | clk: tegra: Model oscillator as clock | Thierry Reding |
2015-04-10 | clk: tegra: Fix typo tabel -> table | Thierry Reding |
2014-11-26 | clk: tegra: Implement memory-controller clock | Thierry Reding |
2013-12-11 | clk: tegra: remove legacy reset APIs | Stephen Warren |
2013-12-11 | clk: tegra: implement a reset driver | Stephen Warren |
2013-11-26 | clk: tegra: add TEGRA_PERIPH_NO_GATE | Peter De Schrijver |
2013-11-26 | clk: tegra: add locking to periph clks | Peter De Schrijver |
2013-11-26 | clk: tegra: Add support for PLLSS | Peter De Schrijver |
2013-11-26 | clk: tegra: introduce common gen4 super clock | Peter De Schrijver |
2013-11-26 | clk: tegra: move PMC, fixed clocks to common files | Peter De Schrijver |
2013-11-26 | clk: tegra: move periph clocks to common file | Peter De Schrijver |
2013-11-26 | clk: tegra: move audio clk to common file | Peter De Schrijver |
2013-11-26 | clk: tegra: add clkdev registration infra | Peter De Schrijver |
2013-11-26 | clk: tegra: add common infra for DT clocks | Peter De Schrijver |
2013-11-26 | clk: tegra: move fields to tegra_clk_pll_params | Peter De Schrijver |
2013-11-26 | clk: tegra: Add TEGRA_PERIPH_NO_DIV flag | Peter De Schrijver |
2013-11-26 | clk: tegra: common periph_clk_enb_refcnt and clks | Peter De Schrijver |
2013-11-26 | clk: tegra: simplify periph clock data | Peter De Schrijver |
2013-06-18 | clk: tegra: T114: add DFLL DVCO reset control | Paul Walmsley |
2013-06-18 | clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL | Paul Walmsley |
2013-06-11 | clk: tegra: Add fields for override bits | Peter De Schrijver |
2013-06-11 | clk: tegra: allow PLL m,n,p init from SoC files | Peter De Schrijver |
2013-05-31 | clk: tegra: Use common of_clk_init function | Prashant Gaikwad |
2013-04-04 | clk: tegra: devicetree match for nvidia,tegra114-car | Peter De Schrijver |
2013-04-04 | clk: tegra: Workaround for Tegra114 MSENC problem | Peter De Schrijver |
2013-04-04 | clk: tegra: Add flags to tegra_clk_periph() | Peter De Schrijver |