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2016-03-20Merge tag 'armsoc-drivers' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs, these contain various things that touch the drivers/ directory but got merged through arm-soc for practical reasons: - Rockchip rk3368 gains power domain support - Small updates for the ARM spmi driver - The Atmel PMC driver saw a larger rework, touching both arch/arm/mach-at91 and drivers/clk/at91 - All reset controller driver changes alway get merged through arm-soc, though this time the largest change is the addition of a MIPS pistachio reset driver - One bugfix for the NXP (formerly Freescale) i.MX weim bus driver" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits) bus: imx-weim: Take the 'status' property value into account clk: at91: remove useless includes clk: at91: pmc: remove useless capacities handling clk: at91: pmc: drop at91_pmc_base usb: gadget: atmel: access the PMC using regmap ARM: at91: remove useless includes and function prototypes ARM: at91: pm: move idle functions to pm.c ARM: at91: pm: find and remap the pmc ARM: at91: pm: simply call at91_pm_init clk: at91: pmc: move pmc structures to C file clk: at91: pmc: merge at91_pmc_init in atmel_pmc_probe clk: at91: remove IRQ handling and use polling clk: at91: make use of syscon/regmap internally clk: at91: make use of syscon to share PMC registers in several drivers hwmon: (scpi) add energy meter support firmware: arm_scpi: add support for 64-bit sensor values firmware: arm_scpi: decrease Tx timeout to 20ms firmware: arm_scpi: fix send_message and sensor_get_value for big-endian reset: sti: Make reset_control_ops const reset: zynq: Make reset_control_ops const ...
2016-03-20Merge tag 'armsoc-arm64' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC 64-bit changes from Arnd Bergmann: "Here's our branch of ARM64 contents for this merge window, now containing all ARM64 changes other than device tree files. - Various new platforms get added: * Allwinner A64 SoC * Annapurna Labs Alpine SoCs * Broadcom Vulcan * Marvell Armada 3700 SoCs * Amlogic S905 - Various defconfig changes to enable platform specific drivers This branch includes the clk git tree to resolve a build-time dependency" * tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) arm64: defconfig: Increase MMC_BLOCK_MINORS to 16 arm64: defconfig: Add Qualcomm sdhci and restart functionality ARM64: Enable Amlogic Meson GXBaby platform arm64: defconfig: Enable Samsung MFD and related configs arm64: alpine: select the Alpine MSI controller driver arm64: defconfig: enable the Alpine family arm64: add Alpine SoC family arm64: defconfig: Enable exynos thermal config arm64: add defconfig options for Allwinner SoCs arm64: defconfig: Enable DesignWare APB GPIO controller arm64: defconfig: Add Renesas R-Car Gen3 USB 2.0 phy driver support arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS clk: samsung: Don't build ARMv8 clock drivers on ARMv7 MAINTAINERS: Add entry for Broadcom Vulcan SoC arm64: cputype info for Broadcom Vulcan arm64: Broadcom Vulcan support arm64: defconfig: Add Broadcom Vulcan to defconfig arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support Documentation: arm: add Marvell Armada 7K and 8K families Documentation: arm: add link to Armada 38x Functional Spec ...
2016-03-20Merge tag 'armsoc-soc' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Arnd Bergmann: "Newly added support for additional SoCs: - Axis Artpec-6 SoC family - Allwinner A83T SoC - Mediatek MT7623 - NXP i.MX6QP SoC - ST Microelectronics stm32f469 microcontroller New features: - SMP support for Mediatek mt2701 - Big-endian support for NXP i.MX - DaVinci now uses the new DMA engine dma_slave_map - OMAP now uses the new DMA engine dma_slave_map - earlyprintk support for palmchip uart on mach-tango - delay timer support for orion Other: - Exynos PMU driver moved out to drivers/soc/ - Various smaller updates for Renesas, Xilinx, PXA, AT91, OMAP, uniphier" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: uniphier: rework SMP code to support new System Bus binding ARM: uniphier: add missing of_node_put() ARM: at91: avoid defining CONFIG_* symbols in source code ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1 ARM: imx: Make reset_control_ops const ARM: imx: Do L2 errata only if the L2 cache isn't enabled ARM: imx: select ARM_CPU_SUSPEND only for imx6 dmaengine: pxa_dma: fix the maximum requestor line ARM: alpine: select the Alpine MSI controller driver ARM: pxa: add the number of DMA requestor lines dmaengine: mmp-pdma: add number of requestors dma: mmp_pdma: Add the #dma-requests DT property documentation ARM: OMAP2+: Add rtc hwmod configuration for ti81xx ARM: s3c24xx: Avoid warning for inb/outb ARM: zynq: Move early printk virtual address to vmalloc area ARM: DRA7: hwmod: Add custom reset handler for PCIeSS ARM: SAMSUNG: Remove unused register offset definition ARM: EXYNOS: Cleanup header files inclusion drivers: soc: samsung: Enable COMPILE_TEST MAINTAINERS: Add maintainers entry for drivers/soc/samsung ...
2016-03-19Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds
Pull ARM updates from Russell King: "Another mixture of changes this time around: - Split XIP linker file from main linker file to make it more maintainable, and various XIP fixes, and clean up a resulting macro. - Decompressor cleanups from Masahiro Yamada - Avoid printing an error for a missing L2 cache - Remove some duplicated symbols in System.map, and move vectors/stubs back into kernel VMA - Various low priority fixes from Arnd - Updates to allow bus match functions to return negative errno values, touching some drivers and the driver core. Greg has acked these changes. - Virtualisation platform udpates form Jean-Philippe Brucker. - Security enhancements from Kees Cook - Rework some Kconfig dependencies and move PSCI idle management code out of arch/arm into drivers/firmware/psci.c - ARM DMA mapping updates, touching media, acked by Mauro. - Fix places in ARM code which should be using virt_to_idmap() so that Keystone2 can work. - Fix Marvell Tauros2 to work again with non-DT boots. - Provide a delay timer for ARM Orion platforms" * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (45 commits) ARM: 8546/1: dma-mapping: refactor to fix coherent+cma+gfp=0 ARM: 8547/1: dma-mapping: store buffer information ARM: 8543/1: decompressor: rename suffix_y to compress-y ARM: 8542/1: decompressor: merge piggy.*.S and simplify Makefile ARM: 8541/1: decompressor: drop redundant FORCE in Makefile ARM: 8540/1: decompressor: use clean-files instead of extra-y to clean files ARM: 8539/1: decompressor: drop more unneeded assignments to "targets" ARM: 8538/1: decompressor: drop unneeded assignments to "targets" ARM: 8532/1: uncompress: mark putc as inline ARM: 8531/1: turn init_new_context into an inline function ARM: 8530/1: remove VIRT_TO_BUS ARM: 8537/1: drop unused DEBUG_RODATA from XIP_KERNEL ARM: 8536/1: mm: hide __start_rodata_section_aligned for non-debug builds ARM: 8535/1: mm: DEBUG_RODATA makes no sense with XIP_KERNEL ARM: 8534/1: virt: fix hyp-stub build for pre-ARMv7 CPUs ARM: make the physical-relative calculation more obvious ARM: 8512/1: proc-v7.S: Adjust stack address when XIP_KERNEL ARM: 8411/1: Add default SPARSEMEM settings ARM: 8503/1: clk_register_clkdev: remove format string interface ARM: 8529/1: remove 'i' and 'zi' targets ...
2016-03-16clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on rk3036Heiko Stuebner
The emac needs constant and very specific rate but the possible PLL-sources are very limited, so we expect the PLL source to be set manually on per board and don't want it to get changed in an automatic way later. So add the necessary clock-id and disable reparenting on set_rate calls. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-16clk: rockchip: associate the rk3036 HCLK_EMAC clock-idXing Zheng
Associate the new clock id the clock. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: Xing Zheng <zhengxing@rock-chips.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: David S. Miller <davem@davemloft.net>
2016-02-22clk: ti: omap3+: dpll: use non-locking version of clk_get_rateTero Kristo
As the code in this file is being executed within irq context in some cases, we must avoid the clk_get_rate which uses mutex internally. Switch the code to use clk_hw_get_rate instead which is non-locking. This fixes an issue where PM runtime will hang the system if enabled with a serial console before a suspend-resume cycle. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com> Fixes: a53ad8ef3dcc ("clk: ti: Convert to clk_hw based provider APIs") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-22clk: samsung: Don't build ARMv8 clock drivers on ARMv7Krzysztof Kozlowski
Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS so it is built also on ARMv7. This does not bring any kind of benefit. There won't be a single kernel image for ARMv7 and ARMv8 SoCs (like multi_v7 for ARMv7). Instead build clock drivers only for respective SoC's architecture. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-18clk: gpio: Really allow an optional clock= DT propertyStephen Boyd
We mis-merged the original patch from Russell here and so the patch went almost all the way, except that we still failed to probe when there wasn't a clocks property in the DT node. Allow that case by making a negative value from of_clk_get_parent_count() into "no parents", like the original patch did. Fixes: 7ed88aa2efa5 ("clk: fix clk-gpio.c with optional clock= DT property") Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-17clk: at91: remove useless includesAlexandre Belloni
Over time, some includes were copy pasted from other clocks drivers but are not necessary. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-02-17clk: at91: pmc: remove useless capacities handlingAlexandre Belloni
Capacities only handles interrupts and they are not use anymore. Remove the whole initialisation. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-02-17clk: at91: pmc: drop at91_pmc_baseAlexandre Belloni
at91_pmc_base is not used anymore, remove it along with at91_pmc_read and at91_pmc_write. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-17ARM: at91: pm: move idle functions to pm.cAlexandre Belloni
Avoid using code from clk/at91 for PM. This also has the bonus effect of setting arm_pm_idle for sama5 platforms. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-02-17clk: at91: pmc: move pmc structures to C fileAlexandre Belloni
pmc.c is now the only user of struct at91_pmc*, move their definition in the C file. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-17clk: at91: pmc: merge at91_pmc_init in atmel_pmc_probeAlexandre Belloni
at91_pmc_init() doesn't do much anymore, merge it in atmel_pmc_probe(). Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-17clk: at91: remove IRQ handling and use pollingAlexandre Belloni
The AT91 clock drivers make use of IRQs to avoid polling when waiting for some clocks to be enabled. Unfortunately, this leads to a crash when those IRQs are threaded (which happens when using preempt-rt) because they are registered before thread creation is possible. Use polling on those clocks instead to avoid the problem. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-02-17clk: at91: make use of syscon/regmap internallyBoris Brezillon
Use the regmap coming from syscon to access the registers instead of using pmc_read/pmc_write. This allows to avoid passing the at91_pmc structure to the child nodes of the PMC. The final benefit is to have each clock register itself instead of having to iterate over the children. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-02-17clk: at91: make use of syscon to share PMC registers in several driversBoris Brezillon
The PMC block is providing several functionnalities: - system clk management - cpuidle - platform suspend Replace the void __iomem *regs field by a regmap (retrieved using syscon) so that we can later share the regmap across several drivers without exporting a new specific API or a global void __iomem * variable. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-16clk: samsung: Enable COMPILE_TEST for Samsung clocksKrzysztof Kozlowski
Enable the COMPILE_TEST to get build coverage of some of Samsung clock controller drivers. Still some of them will be built only if appropriate SoC is chosen (like SOC_EXYNOS4415 or ARCH_S3C64XX). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-16ARM: 8503/1: clk_register_clkdev: remove format string interfaceKees Cook
Many callers either use NULL or const strings for the third argument of clk_register_clkdev. For those that do not and use a non-const string, this is a risk for format strings being accidentally processed (for example in device names). As this interface is already used as if it weren't a format string (prints nothing when NULL), and there are zero users of the format strings, remove the format string interface to make sure format strings will not leak into the clkdev. $ git grep '\bclk_register_clkdev\b' | grep % | wc -l 0 Unfortunately, all the internals expect a va_list even though they treat a NULL format string as special. To deal with this, we must pass either (..., "%s", string) or (..., NULL) so that a the va_list will be created correctly (passing the name as an argument, not as a format string). Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2016-02-12Revert "clk: qcom: Specify LE device endianness"Stephen Boyd
This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87. The commit that caused us to specify LE device endianness here, 29bb45f25ff3 (regmap-mmio: Use native endianness for read/write, 2015-10-29), has been reverted in mainline so now when we specify LE it actively breaks big endian kernels because the byte swapping in regmap-mmio is incorrect. Let's revert this change because it will 1) fix the big endian kernels and 2) be redundant to specify LE because that will become the default soon. Cc: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@baylibre.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10clk: versatile: mask VCO bits before writingLinus Walleij
The Versatile syscon ICST driver OR:s the bits into place but forgets to mask the previous value, making the code only work if the register is zero or giving haphazard results. Mask the 19 bits used by the Versatile syscon interface register. Regression caused and now fixed by yours truly. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Fixes: 179c8fb3c2a6 ("clk: versatile-icst: convert to use regmap") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08Merge tag 'tegra-for-4.5-clk-fixes' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes Pull tegra fixes from Thierry Reding: clk: tegra: Fixes for v4.5-rc3 This set contains a bunch of miscellaneous fixes that have accumulated over the past couple of weeks, primarily for the Tegra210 support added in v4.5-rc1. * tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: super: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warning for pll_m clk: tegra: Use definition for pll_u override bit clk: tegra: Fix warning caused by pll_u failing to lock clk: tegra: Fix clock sources for Tegra210 EMC clk: tegra: Add the APB2APE audio clock on Tegra210 clk: tegra: Add missing of_node_put() clk: tegra: Fix PLLE SS coefficients clk: tegra: Fix typos around clearing PLLE bits during enable clk: tegra: Do not disable PLLE when under hardware control clk: tegra: Fix pllx dyn step calculation clk: tegra: pll: Fix potential sleeping-while-atomic clk: tegra: Fix the misnaming of nvenc from msenc clk: tegra: Fix naming of MISC registers clk: tegra: Remove improper flags for lock_enable clk: tegra: Fix divider on VI_I2C
2016-02-02clk: tegra: super: Fix sparse warnings for functions not declared as staticJon Hunter
Sparse reports the following warnings for structures and functions that should be declared static: drivers/clk/tegra/clk-tegra-super-gen4.c:70:35: warning: symbol 'tegra_super_gen_info_gen4' was not declared. Should it be static? drivers/clk/tegra/clk-tegra-super-gen4.c:96:35: warning: symbol 'tegra_super_gen_info_gen5' was not declared. Should it be static? drivers/clk/tegra/clk-tegra-super-gen4.c:174:13: warning: symbol 'tegra_super_clk_init' was not declared. Should it be static? Fix this by making the above static. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Fix sparse warnings for functions not declared as staticJon Hunter
Sparse reports the following warnings for functions in clk-tegra210.c that should be declared as static: drivers/clk/tegra/clk-tegra210.c:460:6: warning: symbol 'tegra210_pllcx_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:485:6: warning: symbol '_pllc_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:490:6: warning: symbol '_pllc2_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:495:6: warning: symbol '_pllc3_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:500:6: warning: symbol '_plla1_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:510:6: warning: symbol 'tegra210_plla_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:562:6: warning: symbol 'tegra210_plld_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:701:6: warning: symbol 'tegra210_plld2_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:709:6: warning: symbol 'tegra210_plldp_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:722:6: warning: symbol 'tegra210_pllc4_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:731:6: warning: symbol 'tegra210_pllre_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:844:6: warning: symbol 'tegra210_pllx_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:904:6: warning: symbol 'tegra210_pllmb_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:963:6: warning: symbol 'tegra210_pllp_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:1025:6: warning: symbol 'tegra210_pllu_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:1215:15: warning: symbol 'tegra210_clk_adjust_vco_min' was not declared. Should it be static? Fix this by declaring the above as static. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Fix sparse warning for pll_mJon Hunter
Sparse generates the following warning for the pll_m params structure: drivers/clk/tegra/clk-tegra210.c:1569:10: warning: Initializer entry defined twice drivers/clk/tegra/clk-tegra210.c:1570:10: also defined here Fix this by correcting the index for the MISC1 register. Fixes: b31eba5ff3f7 ("clk: tegra: Add support for Tegra210 clocks") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Use definition for pll_u override bitJon Hunter
The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined but not used and when the OVERRIDE bit is cleared in tegra210_pll_init() the code directly uses the bit number. Therefore, use the definition, PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Fix warning caused by pll_u failing to lockJon Hunter
If the pll_u is not configured by the bootloader, then on kernel boot the following warning is seen: clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock tegra_init_from_table: Failed to enable pll_u_out1 ------------[ cut here ]------------ WARNING: at drivers/clk/tegra/clk.c:269 Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-20151214+ #1 Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT) task: ffffffc0bc0a0000 ti: ffffffc0bc0a8000 task.ti: ffffffc0bc0a8000 PC is at tegra_init_from_table+0x140/0x164 LR is at tegra_init_from_table+0x140/0x164 pc : [<ffffffc0008fee78>] lr : [<ffffffc0008fee78>] pstate: 80000045 sp : ffffffc0bc0abd50 x29: ffffffc0bc0abd50 x28: ffffffc00090b8a8 x27: ffffffc000a06000 x26: ffffffc0bc019780 x25: ffffffc00086a708 x24: ffffffc00086a790 x23: ffffffc0006d7188 x22: ffffffc0bc010000 x21: 000000000000016e x20: ffffffc0bc00d100 x19: ffffffc000944178 x18: 0000000000000007 x17: 000000000000000e x16: 0000000000000001 x15: 0000000000000007 x14: 000000000000000e x13: 0000000000000013 x12: 000000000000001a x11: 000000000000004d x10: 0000000000000750 x9 : ffffffc0bc0a8000 x8 : ffffffc0bc0a07b0 x7 : 0000000000000001 x6 : 0000000002d5f0f8 x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000002 x2 : ffffffc000996724 x1 : 0000000000000000 x0 : 0000000000000032 ---[ end trace cbd20ae519e92ced ]--- Call trace: [<ffffffc0008fee78>] tegra_init_from_table+0x140/0x164 [<ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28 [<ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24 [<ffffffc00008291c>] do_one_initcall+0x90/0x194 [<ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8 [<ffffffc000636bb0>] kernel_init+0x10/0xdc [<ffffffc000085cd0>] ret_from_fork+0x10/0x40 clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock tegra_init_from_table: Failed to enable pll_u_out2 ------------[ cut here ]------------ pll_u can be either controlled by software or hardware and this is selected via the OVERRIDE bit in the pll_u base register. In the function tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects hardware control of the pll. However, at the same time the pll_u clocks are populated in the init_table for tegra210 and so software will try to configure the pll_u if it is not already configured and hence, the above warning is seen when the pll fails to lock. Remove the pll_u clocks from the init_table so that software does not try to configure this pll on boot. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Fix clock sources for Tegra210 EMCJon Hunter
The EMC clock sources for Tegra210 currently incorrectly include pll_c2 and pll_c3. However, both of these should have been pll_mb as shown in the TRM. If Tegra210 happens to be configured such that the pll_mb is the default clock for the EMC, as configured by the bootloader, then this will cause a system hang on boot. This is because the kernel will disable the pll_mb when disabling unused clock as it appears to be unused when it is not. Also add the additional pll_p clock source for the EMC. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Add the APB2APE audio clock on Tegra210Jon Hunter
The APB2APE clock for the audio subsystem is required for powering up the audio power domain and accessing the various modules in this subsystem on Tegra210 devices. Add this clock for Tegra210. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Add missing of_node_put()Amitoj Kaur Chawla
for_each_child_of_node() performs an of_node_get() on each iteration, so before breaking out of the loop an of_node_put() is required. Found using Coccinelle. The semantic patch used for this is as follows: // <smpl> @@ expression e; local idexpression child; @@ for_each_child_of_node(root, child) { ... when != of_node_put(child) when != e = child ( return child; | + of_node_put(child); ? return ...; ) ... } // </smpl> Signed-off-by: Amitoj Kaur Chawla <amitoj1606@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Fix PLLE SS coefficientsMark Kuo
The PLLE SS coefficients are different between Tegra210 and Tegra114. Add SoC generation specific versions for Tegra114 and Tegra210 and use them in their respective ->enable() callbacks. Signed-off-by: Mark Kuo <mkuo@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Fix typos around clearing PLLE bits during enableRhyland Klein
While enabling PLLE on both Tegra114 and Tegra210, we should be clearing PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting them. This patch fixes both places where we incorrectly set instead of cleared those bits. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Do not disable PLLE when under hardware controlMark Kuo
Software should not disable PLLE if PLLE is already put under hardware control. Signed-off-by: Mark Kuo <mkuo@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Fix pllx dyn step calculationRhyland Klein
The logic for calculating the input rate used when figuring out the proper dynamic steps for pllx was incorrect. It is supposed to be calculated using parent_rate / m but it was just using the parent rate directly, therefore using the wrong step values. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: pll: Fix potential sleeping-while-atomicAndrew Bresticker
Since the ->enable() callback is called with a spinlock held, we cannot call potentially blocking functions such as clk_get_rate() or clk_get_parent(), so use the unlocked versions instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> [rklein: Adapted from ChromeOS patch, removing pllu_enable cleanup as it isn't present upstream] Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Fix the misnaming of nvenc from msencRhyland Klein
When adding the nvenc clock, it was partially named msenc in the code. Since the msenc clock isn't present in Tegra210 and has been replaced by the nvenc clock, its misleading to see it present. Therefore, properly rename it. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02clk: tegra: Fix naming of MISC registersRhyland Klein
Some register for PLLM and PLLMB were named MISC0 but according to the TRM, they have different names. Sync up the names to make it easier to understand which register they are really referring to. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-01ARM: pxa: define clock registers as __iomemArnd Bergmann
We should not dereference registers as pointers, so use readl/writel instead for these registers. The clock registers are accessed in multiple files, so we have to change them all at once. I stumbled over these registers while looking at something unrelated. There are in fact other registers with the same problem, but I did not try to address those at this point. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2016-01-29Merge tag 'v4.5-rockchip-clkfixes1' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes Pull rockchip fixes from Heiko Stuebner: Fixes for wrong register offsets in both rk3036 and rk3368. Also rename the external input for the emac on rk3036, which should still be ok to do, as that binding was only introduced during this merge-window. * tag 'v4.5-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3368: fix some clock gates clk: rockchip: rk3036: rename emac ext source clock clk: rockchip: rk3036: fix the div offset for emac clock clk: rockchip: rk3036: fix uarts clock error clk: rockchip: rk3036: fix the FLAGs for clock mux
2016-01-29clk: Move vendor's Kconfig into CCF menu sectionJames Liao
Move all vendor's Kconfig into CCF menu section to prevent new drivers putting their Kconfig files in a wrong place. Some Kconfigs need to be modified at the same time to avoid build warnings. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> [sboyd@codeaurora.org: Fix typos in commit message] Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: mediatek: Fix memory leak on clock init failJames Liao
mtk_clk_register_composite() may leak memory due to some error handling path don't free all allocated memory. This patch free all pointers that may allocate memory before error return. And it's safe because kfree() can handle NULL pointers. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: move the common clock's to_clk_*(_hw) macros to clk-provider.hGeliang Tang
to_clk_*(_hw) macros have been repeatedly defined in many places. This patch moves all the to_clk_*(_hw) definitions in the common clock framework to public header clk-provider.h, and drop the local definitions. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: xgene: Remove return from void functionStephen Boyd
This function doesn't return anything because it's void. Drop the return statement. Cc: Loc Ho <lho@apm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: xgene: Add SoC and PMD PLL clocks with v2 hardwareLoc Ho
Add X-Gene SoC and PMD PLL clocks support for v2 hardware. X-Gene SoC v2 and above use an slightly different SoC and PMD PLL hardware logic. Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: s2mps11: remove redundant codeAndi Shyti
The definition of s2mps11_name is meant to resolve the name of a given clock. Remove it because the clocks have the same name we can get it directly from the s2mps11_clks_init structure. While in the probe function the s2mps11_clks is used only to iterate through the s2mps11_clks. The naming itself brings confusion and the readability does not improve much. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: s2mps11: remove redundant static variables declarationAndi Shyti
The clk_table and clk_data are declared static. The clk_table contains the three clock data structures belonging to the s2mps11 driver. In the probe function it gets stored into clk_data. Remove clk_table and refer directly to clk_data. clk_data, itself, is also declared static. Declare locally it and allocate it inside the probe function, as it is not used anywhere else. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: s2mps11: allocate only one structure for clock initAndi Shyti
The driver allocates three structures, s2mpsxx_clk_init, for three different clock types (s2mps11, s2mps13 and s2mps14). They are quite similar but they differ only by the name. Only one of these structures is used, while the others lie unused in the memory. The clock's name, though, is not such a meaningful information and by assigning the same name to the initial data we can avoid over allocation. The common name chosen will be s2mps11, coherently with the device driver name, instead of the clock device. Therefore, remove the structures associated to s2mps13 and s2mps14 and use only the one referred to s2mps11 for all kind of clocks. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Suggested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: s2mps11: merge two for loops in oneAndi Shyti
The driver already loops once, there is no reason to loop again for a different purpose. Merge the second loop into the first. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk-divider: make sure read-only dividers do not write to their registerHeiko Stuebner
Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed the special ops struct for read-only clocks and instead opted to handle them inside the regular ops. On the rk3368 this results in breakage as aclkm now gets set a value. While it is the same divider value, the A53 core still doesn't like it, which can result in the cpu ending up in a hang. The reason being that "ACLKENMasserts one clock cycle before the rising edge of ACLKM" and the clock should only be touched when STANDBYWFIL2 is asserted. To fix this, reintroduce the read-only ops but do include the round_rate callback. That way no writes that may be unsafe are done to the divider register in any case. The Rockchip use of the clk_divider_ops is adapted to this split again, as is the nxp, lpc18xx-ccu driver that was included since the original commit. On lpc18xx-ccu the divider seems to always be read-only so only uses the new ops now. Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-05 10:28:50 +0000