Age | Commit message (Collapse) | Author |
|
When taking dump of tegra gpio through debug FS, also prints the
gpio port name like A, B, C, etc. for easy understanding.
Change-Id: I38af2f7c696ad7633456be5ca1f8c164edcd94f6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/361532
|
|
Bug 1237374
Change-Id: Id328c81193eb0e2d44123cd45c8de7ce400e95b3
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/200298
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
|
|
Pass of_node pointer to to gpio chip when device registered through
DT.
Change-Id: Ie5210379789e0b4a2d42ba693601ee528133a99f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/356510
|
|
Alias the gpio base number when registering the device
from DT. This will help on assigning the base gpio number
to gpio controller so that non-dt client of gpio can use
these gpios.
Change-Id: I12ce2108d21d21fa7c9a0c60d498d4136515add2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/356512
|
|
To help on debugging the gpio device registration, enable prints
for alloated range of gpio to the gpio device.
Change-Id: I7a0cef54220cf5c4bf1c6bd58d19c0443be8f293
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/356511
|
|
Change-Id: I0c919e55654e0c224a5f8a5df80d9f49e92dbb37
|
|
Move of_gpiochip_add outof spin_lock, since kzalloc inside
of_gpiochip_add -> of_gpiochip_add_pin_range -> gpiochip_add_pin_range -> kzalloc
WARNING: at kernel/lockdep.c:2740 lockdep_trace_alloc+0xf8/0xfc()
DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The current implementation of desc_to_gpio() relies on the chip pointer
to be set to a valid value in order to compute the GPIO number. This
was done in the hope that we can get rid of the gpio_desc global array,
but this is not happening anytime soon.
This patch reimplements desc_to_gpio() in a fashion similar to that of
gpio_to_desc(). As a result, desc_to_gpio(gpio_to_desc(gpio)) == gpio is
now always true. This allows to call desc_to_gpio() on non-initialized
descriptors as some error-handling code currently does.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reported-by: Dr. H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
This is the 3.10.24 stable release
Change-Id: Ibd2734f93d44385ab86867272a1359158635133b
|
|
commit 1aeef303b5d9e243c41d5b80f8bb059366514a10 upstream.
For MPC8572/MPC8536, the status of GPIOs defined as output
cannot be determined by reading GPDAT register, so the code
use shadow data register instead. But the code may give the
wrong status of GPIOs defined as input under some scenarios:
1. If some pins were configured as inputs and were asserted
high before booting the kernel, the shadow data has been
initialized with those pin values.
2. Some pins have been configured as output first and have
been set to the high value, then reconfigured as input.
The above cases will make the shadow data for those input
pins to be set to high. Then reading the pin status will
always return high even if the actual pin status is low.
The code should eliminate the effects of the shadow data to
the input pins, and the status of those pins should be
read directly from GPDAT.
Acked-by: Scott Wood <scottwood@freescale.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
commit 2ba3154d9cb13697b97723cce75633b48adfe826 upstream.
The PL061 driver had the irqdomain initialization in an unfortunate
place: when used with device tree (and thus passing the base IRQ
0) the driver would work, as this registers an irqdomain and waits
for mappings to be done dynamically as the devices request their
IRQs, whereas when booting using platform data the irqdomain core
would attempt to allocate IRQ descriptors dynamically (which works
fine) but also to associate the irq_domain_associate_many() on all
IRQs, which in turn will call the mapping function which at this
point will try to set the type of the IRQ and then tries to acquire
a non-initialized spinlock yielding a backtrace like this:
CPU: 0 PID: 1 Comm: swapper Not tainted 3.13.0-rc1+ #652
Backtrace:
[<c0016f0c>] (dump_backtrace) from [<c00172ac>] (show_stack+0x18/0x1c)
r6:c798ace0 r5:00000000 r4:c78257e0 r3:00200140
[<c0017294>] (show_stack) from [<c0329ea0>] (dump_stack+0x20/0x28)
[<c0329e80>] (dump_stack) from [<c004fa80>] (__lock_acquire+0x1c0/0x1b80)
[<c004f8c0>] (__lock_acquire) from [<c0051970>] (lock_acquire+0x6c/0x80)
r10:00000000 r9:c0455234 r8:00000060 r7:c047d798 r6:600000d3 r5:00000000
r4:c782c000
[<c0051904>] (lock_acquire) from [<c032e484>] (_raw_spin_lock_irqsave+0x60/0x74)
r6:c01a1100 r5:800000d3 r4:c798acd0
[<c032e424>] (_raw_spin_lock_irqsave) from [<c01a1100>] (pl061_irq_type+0x28/0x)
r6:00000000 r5:00000000 r4:c798acd0
[<c01a10d8>] (pl061_irq_type) from [<c0059ef4>] (__irq_set_trigger+0x70/0x104)
r6:00000000 r5:c01a10d8 r4:c046da1c r3:c01a10d8
[<c0059e84>] (__irq_set_trigger) from [<c005b348>] (irq_set_irq_type+0x40/0x60)
r10:c043240c r8:00000060 r7:00000000 r6:c046da1c r5:00000060 r4:00000000
[<c005b308>] (irq_set_irq_type) from [<c01a1208>] (pl061_irq_map+0x40/0x54)
r6:c79693c0 r5:c798acd0 r4:00000060
[<c01a11c8>] (pl061_irq_map) from [<c005d27c>] (irq_domain_associate+0xc0/0x190)
r5:00000060 r4:c046da1c
[<c005d1bc>] (irq_domain_associate) from [<c005d604>] (irq_domain_associate_man)
r8:00000008 r7:00000000 r6:c79693c0 r5:00000060 r4:00000000
[<c005d5d0>] (irq_domain_associate_many) from [<c005d864>] (irq_domain_add_simp)
r8:c046578c r7:c035b72c r6:c79693c0 r5:00000060 r4:00000008 r3:00000008
[<c005d814>] (irq_domain_add_simple) from [<c01a1380>] (pl061_probe+0xc4/0x22c)
r6:00000060 r5:c0464380 r4:c798acd0
[<c01a12bc>] (pl061_probe) from [<c01c0450>] (amba_probe+0x74/0xe0)
r10:c043240c r9:c0455234 r8:00000000 r7:c047d7f8 r6:c047d744 r5:00000000
r4:c0464380
This moves the irqdomain initialization to a point where the spinlock
and GPIO chip are both fully propulated, so the callbacks can be used
without crashes.
I had some problem reproducing the crash, as the devm_kzalloc():ed
zeroed memory would seemingly mask the spinlock as something OK,
but by poisoning the lock like this:
u32 *dum;
dum = (u32 *) &chip->lock;
*dum = 0xaaaaaaaaU;
I could reproduce, fix and test the patch.
Reported-by: Russell King <linux@arm.linux.org.uk>
Cc: Rob Herring <robherring2@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
commit 0c8aab8e65e450f2bfea494c1b6a86ded653f88c upstream.
It's not obvious from the label name but "err1" tries to release
"p->irq_domain" which leads to a NULL dereference.
Fixes: 119f5e448d32 ('gpio: Renesas R-Car GPIO driver V3')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
commit d535922691fc026479fcc03e78ac3d931a54e75a upstream.
There is a bug in mvebu_gpio_probe() where we do:
mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
if (mvchip->irqbase < 0) {
The problem is that mvchip->irqbase is unsigned so the error handling
doesn't work. I have changed it to be a regular int.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
commit 0b2aa8bed3e13892fcac77e4f50ec6e80125469d upstream.
Commit c111feabe2e2 (gpio: twl4030: Cache the direction and output
states in private data) improved things in general, but caused a
regression for setting the GPIO output direction.
The change reorganized twl_direction_out() and twl_set() and swapped
the function names around in the process. While doing that, a bug got
introduced that's not obvious while reading the patch as it appears
as no change to the code.
The bug is we now call function twl4030_set_gpio_dataout() twice in
both twl_direction_out() and twl_set(). Instead, we should first
call twl_direction_out() in twl_direction_out() followed by
twl4030_set_gpio_dataout() in twl_set().
This regression probably has gone unnoticed for a long time as the
bootloader may have set the GPIO direction properly in many cases.
This fixes at least the LCD panel not turning on omap3 LDP for
example.
Cc: linux-gpio@vger.kernel.org
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
The ams AS3722 gpio functionality is moved to pinctrl-as3722 driver
and hence removing this driver.
Change-Id: Iffb9cd047c879ffddd4db484c4db54d6292e7444
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/328692
Reviewed-by: Automatic_Commit_Validation_User
|
|
For initialisation of the GPIO based on DT data, it allocates memory.
Hence calling the gpio initialisation based on dt node on non-atomic
context.
bug 1400884
Change-Id: I69b7a4be980078c1fa5e5e43f9c7bf24ecb97dd2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/327106
GVS: Gerrit_Virtual_Submit
|
|
commit 03d152d5582abc8a1c19cb107164c3724bbd4be4 upstream.
Checking LP_INT_STAT is not enough in the interrupt handler because its
contents get updated regardless of whether the pin has interrupt enabled or
not. This causes the driver to loop forever for GPIOs that are pulled up.
Fix this by checking the interrupt enable bit for the pin as well.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
This is the 3.10.17 stable release
Conflicts:
drivers/usb/host/xhci.c
Change-Id: I6bd3b15ff92a0b94568b9d02e9bb1036becfca20
|
|
Moving mach-tegra/gic.h and mach-tegra/pm-irq.h to
include/linux/irqchip/tegra-irq.h so that it helps faclitate the
movement of irq drivers from mach-tegra/ to drivers/.
Bug 1379891
Change-Id: Id062ebc16441ac295df78731c1e44b32e75d3286
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/302884
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Register syscore ops for modules whose context has to
saved/restore during entry/exit to LP0 state from CPU
Idle.
Bug 1254633
Change-Id: Idf4a67535754db3ccc2fc528469fb17ec198cee0
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299447
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
commit fac7fa162a19100298d5d91359960037dc5bfca9 upstream.
The OMAP GPIO controller HW requires a pin to be configured in GPIO
input mode in order to operate as an interrupt input. Since drivers
should not be aware of whether an interrupt pin is also a GPIO or not,
the HW should be fully configured/enabled as an IRQ if a driver solely
uses IRQ APIs such as request_irq(), and never calls any GPIO-related
APIs. As such, add the missing HW setup to the OMAP GPIO controller's
irq_chip driver.
Since this bypasses the GPIO subsystem we have to ensure that another
driver won't be able to request the same GPIO pin that is used as an
IRQ and set its direction as output. Requesting the GPIO and setting
its direction as input is allowed though.
This fixes smsc911x ethernet support for tobi and igep OMAP3 boards
and OMAP4 SDP SPI based ethernet that use a GPIO as an interrupt line.
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: George Cherian <george.cherian@ti.com>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Tested-by: Lars Poeschel <poeschel@lemonage.de>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
commit fa365e4d729065b5e85165df3dc9699ed47489cc upstream.
The GPIO OMAP controller pins can be used as IRQ and GPIO
independently so is necessary to keep track GPIO pins and
IRQ lines usage separately to make sure that the bank will
always be enabled while being used.
Also move gpio_is_input() definition in preparation for the
next patch that setups the controller's irq_chip driver when
a caller requests an interrupt line.
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: George Cherian <george.cherian@ti.com>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Tested-by: Lars Poeschel <poeschel@lemonage.de>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
Add support to provide the list of GPIOs which need to be
set as input, output with low and output with high.
These values will be provided from DTS and GPIOs are configured
during registration with gpiolibs.
Change-Id: If46fa55311265707133eb80ce3fe80684a97af6e
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/280741
(cherry picked from commit 61eef7b8a888337fc451714ef3604fd505002639)
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
|
|
This is used when gpio core wants to print the message
using dev_*.
Change-Id: I033375b5af8d4df731bf11dba9662798b44dcab8
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/280740
(cherry picked from commit 5b238b4c6d75ea80df5cbdb388fad3fe1e2906c4)
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
|
|
Fix following comiplation warning:
---
gpio/gpio-palmas.c: In function 'palmas_gpio_input':
gpio/gpio-palmas.c:128:3: warning: format '%d' expects a matching 'int' argument [-Wformat]
gpio/gpio-palmas.c: In function 'palmas_gpio_set_debounce':
gpio/gpio-palmas.c:159:3: warning: format '%d' expects a matching 'int' argument [-Wformat]
gpio/gpio-palmas.c: At top level:
gpio/gpio-palmas.c:140:12: warning: 'palmas_gpio_set_debounce' defined but not used [-Wunused-function]
---
Change-Id: Ieeec586a9ec084d01d6f62fa1fe01a04c5850d05
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/270072
|
|
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Change-Id: I13f3ff891510d2c868f609d507149b32183d34c5
|
|
We don't use this driver on any supported downstream platforms
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Change-Id: I1f082cdb4f14a7e6dfc1d0b4aa07325102d99ab2
Reviewed-on: http://git-master/r/270001
|
|
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Change-Id: I082f222945f054b585659cbd65d042d45e3cd225
Reviewed-on: http://git-master/r/269997
|
|
Align the Palmas GPIO driver to mainline and keep
porting TPS80036 device on this driver.
This will also add DT support on this driver.
Change-Id: Ib63050d1cd9fc29c9f9754ff27385b100df6dcc7
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/269138
|
|
Bug 1352814
Change-Id: I44752c2f453e9accb594a8c0c250cbd48165c703
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/264238
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
fix build issue with as3722 gpio
Bug 1275005
Change-Id: Iec79992ad04dd462565906c8eb377c95beec1eec
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/232840
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
|
|
AS3722 is a PMIC with multiple DCDC and LDO power supplies,
GPIOs, an RTC, WDT. This patch adds support for gpio
Change-Id: Iac350b2942b5b07f7355b7abd8acb22ae5dc5a04
Signed-off-by: Florian Lobmaier <florian.lobmaier@ams.com>
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/225578
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
|
|
Moving tegra gpio suspend/resume from platform suspend to syscore
suspend/resume.Since GPIO's are need by other modules in the kernel
and it state cannot be maintained across the power cycle ,it needs to
be suspended furthur in time and hence cannot be sheduled along with
other drivers.Hence,moving to Syscore suspend allows the GPIO module
to be suspend later and resume futher ahead of the devices.
Bug 1323103
Change-Id: Id3a092a1e492f2830c485b330ccc6fb26746ff6d
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/213997
(cherry picked from commit bc25f5333f90baf716b313060d56dd78fe7fe7e9)
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/246721
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Tested-by: Dan Willemsen <dwillemsen@nvidia.com>
|
|
We're not using pinctrl yet, so don't make gpio-tegra require it.
Without this change, gpio_request will always return -EPROBE_DEFER.
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
|
|
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
|
|
|
|
This allows setting wakeups in LP1 that are not available
in for LP0.
Bug 1261915
Change-Id: Ic8f7c07065c0eb53bb0564d022e36a172924451d
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/216363
(cherry picked from commit 9a8a4923a871d5084b61e500d684f519f6495adf)
Reviewed-on: http://git-master/r/226436
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Tested-by: Karthik Ramakrishnan <karthikr@nvidia.com>
|
|
Enable gpio-palmas driver to retrieve value of pins
in both INPUT as well as OUTPUT modes
Bug 1232690
Change-Id: Icadfa8f8521224268acf505e4a74aab34656503d
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/220215
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
Added support to read write GPIO8 to GPIO15 registers
Change-Id: Ia8687cbc193c6b0934ae44ebafe62c89fb1c19a7
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/209992
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
To get the irq number for given gpio, use the palmas API
palmas_irq_get_virq() in place of directly using regmap API.
Change-Id: I2305b6c6c852a914efd08c4e020dba4301bd83fc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/208339
(cherry picked from commit 6fc336cce326023d27d5ce311f79480b990714f1)
Reviewed-on: http://git-master/r/209989
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Sumit Sharma <sumsharma@nvidia.com>
|
|
Added support for more number of GPIOs for TPS80036
Change-Id: I6eab1c4ba65182a5d968b60349a972a4cf6e67cd
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/200397
(cherry picked from commit e64966e899fd810f40840fb1212bdfff3d6fc04f)
Reviewed-on: http://git-master/r/205424
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
|
|
As per ES1.0 errata, debaunce of GPIO1 does not work. Returning the error
in this case.
bug 1228630
Change-Id: I836951d6e9cf7d11679226abb2b4add7f4f03268
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198066
|
|
Bug 1178629
Change-Id: Iba2dff0ce54150b93c7f9389f5b43c190d4130d7
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/194995
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
|
|
The argument of max77660_reg_update() take the val first and
then mask. Pass parameters in correct sequence.
Change-Id: Ieb2d20a78eb0afd798dcdfa6b99442a56fc95e87
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/194730
|
|
Remove pin control configuration and initialization from gpio
driver as this is moved to pincontrol driver.
Change-Id: I16cfa8346d5b3bae77d1c6beef2581af5adedd44
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/194715
|
|
Use regmap irq for interrupt support in place of implementing the
same locally. This reduces code duplication.
Change-Id: If2daa29464ec6606d1da69b4c2578e9c8e484dfd
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/194663
|
|
-Remove register caching.
-Use max77660_reg_* api's for io operations.
-Correct AME register address.
Bug 1210609
Bug 1221126
Change-Id: I6f3c4f772b594435cbe1477b7154190d570dc15f
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/194398
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
|
|
Eanble/disable the bank irq wakes based on wake-depth which
directly related to the number of gpios on that bank are
wake enabled/disabled.
bug 1230573
Change-Id: I94fc8cb8dac890bdd3a07e82ad9d5a58004d6b82
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198804
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
|
|
Change-Id: Ib649e5aac02d9d2e855381c71cc946b52617880d
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/161907
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
|
|
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
|